k4h281638d Samsung Semiconductor, Inc., k4h281638d Datasheet - Page 27
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k4h281638d
Manufacturer Part Number
k4h281638d
Description
128mb D-die X16 Ddr Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4H281638D.pdf
(52 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
k4h281638d-TCA2
Manufacturer:
SAMSUNG
Quantity:
660
128Mb D-die(x16) DDR SDRAM
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required:
1. The BST command may only be issued on the rising edge of the input clock, CK.
2. BST is only a valid command during Read bursts.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same
4.
5. Refer to "3.3.2 Burst write operation"
the clock(CK). The burst stop command has the fewest restrictions making it the easiest method to use when
terminating a burst read operation before it has been completed. When the burst stop command is issued dur-
ing a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which
is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported dur-
ing a write burst operation.
3.3.9 Burst Stop
CAS Latency=2
CAS Latency=2.5
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of
bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and
ends on the rising clock edge that strobes in the Bank Activate command. During write with
autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command without interrupting the Write burst as described in 1 above.
Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min)
must still be satisfied such that a Write with autoprecharge command has the same timing as a Write
command followed by the earliest possible Precharge command which does not interrupt the burst.
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to
< Burst Length=4, CAS Latency= 2, 2.5 >
Command
CK
CK
DQS
DQ s
DQS
DQ s
READ A
0
Burst Stop
1
Figure 17. Burst stop timing
NOP
Dout 0 Dout 1
2
- 27 -
Dout 0 Dout 1
NOP
The burst ends after a delay equal to the CAS latency.
3
NOP
4
NOP
5
REV. 0.6 Oct. 21. 2002
NOP
6
NOP
7
NOP
8