k4h281638d Samsung Semiconductor, Inc., k4h281638d Datasheet - Page 45

• Manufacturer Part Number: k4h281638d
• Description: 128mb D-die X16 Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

128Mb D-die(x16) DDR SDRAM
AC Timming Parameters & Specifications
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/ C K
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/ C K
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
Output Slew Rate Matching Ratio(rise to fall)
Parameter
CL=2.0
CL=2.5
Symbol
tDQSCK
tWPRES
tDQSQ
tWPRE
tSL(IO)
tRPRE
tDQSS
tDQSH
tDQSL
tSLMR
tRPST
tSL(O)
tWTR
tRAS
tRCD
tRRD
tCCD
tDSS
tDSH
tDSC
tSL(I)
tRFC
tWR
tRC
tCH
tRP
tCK
tCL
tAC
tHZ
tLZ
tIS
tIH
tIS
tIH
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.75
0.67
-0.6
-0.7
-0.7
-0.7
7.5
0.9
0.4
0.2
0.2
0.9
0.8
0.8
0.5
0.5
1.0
60
72
42
18
18
12
15
(DDR333)
1
1
6
0
-
-TCB3
- 45 -
Max
0.55
0.55
+0.6
+0.7
0.45
1.25
+0.7
+0.7
70K
1.1
0.6
1.1
4.5
1.5
1 2
1 2
-0.75
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
(DDR266A)
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
0.5
0.5
1.0
6 5
7 5
4 5
2 0
2 0
1 5
1 5
1
1
0
-
-TCA2
120K
+0.75
+0.75
Max
+0.75
+0.75
0.55
0.55
1.25
0.5
1.1
0.6
1.1
4.5
1.5
1 2
1 2
-0.75
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
(DDR266B)
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
0.5
0.5
1.0
6 5
7 5
4 5
2 0
2 0
1 5
1 5
1 0
1
1
0
-
-TCB0
REV. 0.6 Oct. 21. 2002
+0.75
+0.75
Max
120K
+0.75
+0.75
0.55
0.55
1.25
0.5
1.1
0.6
1.1
4.5
1.5
1 2
1 2
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
-0.8
-0.8
0.9
0.4
0.2
0.2
0.9
1.1
1.1
1.1
1.1
-0.8
-0.8
0.5
0.5
1.0
7 0
8 0
4 8
2 0
2 0
1 5
1 5
1 0
1
1
0
(DDR200)
-
-TCA0
Max
120K
+0.8
+0.8
0.55
0.55
1.25
+0.8
+0.8
0.6
1.1
0.6
1.1
4.5
1.5
12
Unit Note
V/ns
V/ns
V/ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
5
5
2
6
6
6
6
6
7