hcts273ms Intersil Corporation, hcts273ms Datasheet

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hcts273ms

Manufacturer Part Number
hcts273ms
Description
Radiation Hardened Octal D Flip-flop
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS273MS is a Radiation Hardened octal D flip-
flop, positive edge triggered, with reset.
The HCTS273MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS273MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS273DMSR
HCTS273KMSR
HCTS273D/Sample
HCTS273K/Sample
HCTS273HMSR
Day (Typ)
- Bus Driver Outputs - 15 LSTTL Loads
- VIL = 0.8V Max
- VIH = VCC/2 Min
PART NUMBER
|
Copyright
10
©
RAD (Si)/s. 20ns Pulse
Intersil Corporation 1999
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/Bit-
1
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
HCTS273MS
SCREENING LEVEL
Pinouts
GND
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
Radiation Hardened
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Octal D Flip-Flop
Spec Number
20
19
18
17
16
15
14
13
12
11
File Number
20
19
18
17
16
15
14
13
12
PACKAGE
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
518642
2274.2
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP

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hcts273ms Summary of contents

Page 1

... VIH = VCC/2 Min • Input Current Levels VOL, VOH Description The Intersil HCTS273MS is a Radiation Hardened octal D flip- flop, positive edge triggered, with reset. The HCTS273MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. ...

Page 2

... RESET (MR NOTE The level of Q established by the last low to high transition of the clock H = High Level L = Low Level X = Immaterial = Transition from low to high HCTS273MS ...

Page 3

... VCC = 4.5V, VIH =2.25V, Functional Test VIL =0.8V (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS273MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 4

... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCTS273MS GROUP (NOTES 1, 2) ...

Page 5

... Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate Group A testing in accordance with method 5005 of MIL-STD-883 may be exercised. Specifications HCTS273MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP DELTA LIMIT 5 5 -15 Hour TABLE 6 ...

Page 6

... Each pin except VCC and GND will have a resistor of 680 OPEN 12, 15, 16, 19 NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS273MS TABLE 7. TOTAL DOSE IRRADIATION TEST PRE RAD POST RAD ...

Page 7

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS273MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 8

... TSU( FIGURE 3. DATA SET-UP AND HOLD TIMES AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS273MS INPUT LEVEL TPLH Q VS FIGURE 2. MASTER RESET PULSE WIDTH. MASTER RESET TO OUTPUT DELAY AND MASTER RESET TO CLOCK RECOVERY TIME VS VS TH(H) VOH TSU(H) VS VOL FIGURE 4 ...

Page 9

... D1 (4) Q1 (5) Q2 (6) D2 (7) (8) D3 NOTE: The die diagram is a generic plot form a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCTS273 is TA14407. HCTS273MS HCTS273MS Q0 MR VCC Q7 (2) (1) (20) (19) (9) (10) ...

Page 10

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 727-9207 FAX: (407) 724-7240 HCTS273MS EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...

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