msm548263 Oki Semiconductor, msm548263 Datasheet - Page 31

• Manufacturer Part Number: msm548263
• Description: Msm548263256k X 8 Multiport Dram
• Manufacturer: Oki Semiconductor

¡ Semiconductor
MSM548263
If the DSF is "high" at the falling edge of RAS, special functions such as split transfer, flash write,
load mask register, load color register, CBRS and CBRN can be invoked.
If the DSF is "low" at the falling edge of RAS and "high" at the falling edge of CAS, the block write
feature can be invoked.
RAM PORT OPERATION
Extended RAM Read Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L"
CAS falling edge --- DSF = "L"
The MSM548263 offers an accelerated page mode cycle (EXTENDED PAGE MODE) by eliminating
output disable from CAS "high", and it allows CAS precharge time (t
) to occur without the
CP
output data becoming invalid. This new data out operates (Extended data out) as any RAM read
or Page Mode Read, except data will be held valid after CAS goes "high", as long as RAS is "low".
RAM Write Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L"
CAS falling edge --- DSF = "L"
1) Write cycle with no mask: RAS falling edge -- WE = "H"
If WE is set "low" at the falling edge of CAS after RAS goes "low", a write cycle is excuted. If WE
is set "low" before the CAS falling edge, this cycle becomes an early write cycle, and all DQ pins
attain high impedance. All 8 data are latched on the falling edge of CAS.
If WE is set "low" after the CAS falling edge, this cycle becomes a late write cycle, and all 8 data
are latched on the falling edge of WE.
2) Write cycle with mask: RAS falling edge -- WE = "L"
If WE is set "low" at the falling edge of RAS, two modes of mask write can be invoked.
#1 In new mask mode mask data is loaded and used. The mask data on DQ1 - DQ8 is latched into
the write mask register at the falling edge of RAS. When the mask data is low, writing is inhibited
into the RAM and the mask data is high, data is written into the RAM. This mask data is in effect
during the RAS cycle. In page mode cycle the mask data is retained during page access.
#2 If a load mask register cycle (LMR) has been performed, the mask data is not loaded from DQ
pins, and the mask data stored in the mask register is persistently used.
This operation is known as persistent write mask, set by LMR and reset by CBRR.
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