msm548263 Oki Semiconductor, msm548263 Datasheet - Page 32

• Manufacturer Part Number: msm548263
• Description: Msm548263256k X 8 Multiport Dram
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Load/Read Color Register: RAS falling edge --- CAS = TRG = WE = DSF = "H"
The MSM548263 is provided with an on-chip 8-bit color register for use during the flash write or
block write operation. Each bit of the color register corresponds to one of the DRAM I/O blocks.
The data presented on the DQi lines is subsequently latched into the color register at the falling
edge of either CAS or WE whichever occurs later.
The read color register cycle is activated by holding WE "high" at the falling edge of CAS, and
throughout the remainder of the cycle. The data in the color register becomes valid on the DQi
lines after the specified access times from RAS and TRG are satisfied.
During the load/read color register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.
Load/Read Mask Register:
The MSM548263 is provided with an on-chip 8-bit mask register for use during the mask write
cycle, flash write cycle, block write cycle, masked write transfer, and masked split write transfer.
Each bit of the mask register corresponds to one of the DRAM I/O blocks.
The data presented on the DQi lines is subsequently latched into the mask register at the falling
edge of either CAS or WE whichever occurs later.
The read mask register cycle is activated by holding WE "high" at the falling edge of CAS, and
throughout the remainder of the cycle. The data in the mask register becomes valid on the DQi
lines after the specified access times from RAS and TRG are satisfied.
During the load/read mask register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.
Flash Write: RAS falling edge --- CAS = TRG = DSF = "H", WE = "L"
Flash write allows for the data in the color register to be written into all the memory locations of
a selected row.
Each bit of the color register corresponds to one of the DRAM I/O blocks. The flash write
operation can be selectively controlled on an I/O basis in the same manner as the write per bit
operation. The mask data is the same as that of a RAM write cycle.
CAS falling edge --- DSF = "H"
RAS falling edge --- CAS = TRG = WE = DSF = "H"
CAS falling edge --- DSF = "L"
MSM548263
32/40