k9f5608u0a-ycb0 Samsung Semiconductor, Inc., k9f5608u0a-ycb0 Datasheet - Page 21

• Manufacturer Part Number: k9f5608u0a-ycb0
• Description: Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10 s(t
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column
address(column 511 or 527 depending on the state of GND input pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10 s
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way the Read1
and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be
selectively accessed by writing the Read2 command with GND input pin low. Addresses A
spare area while addresses A
sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com-
mand(00h/01h) is needed to move the pointer back to the main area. Figures 3 through 6 show typical sequence and timings for
each read operation.
K9F5608U0A-YCB0,K9F5608U0A-YIB0
Figure 3. Read1 Operation
CLE
CE
WE
ALE
R/B
RE
I/O
0
~
7
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
00h
Start Add.(3Cycle)
A
4
0
to A
~ A
7
7
& A
are ignored. Unless the operation is aborted, the page address is automatically incremented for
9
~ A
24
R
). The system controller can detect the completion of this data transfer(tR) by analyz-
1st half array
t
R
(00h Command)
Data Field
2st half array
21
Spare Field
Data Output(Sequential)
1st half array
0
to A
(01h Command)*
Data Field
FLASH MEMORY
3
set the starting address of the
2st half array
Spare Field