k9f5608u0a-ycb0 Samsung Semiconductor, Inc., k9f5608u0a-ycb0 Datasheet - Page 3

• Manufacturer Part Number: k9f5608u0a-ycb0
• Description: Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9F5608U0A-YCB0,K9F5608U0A-YIB0
Figure 2. ARRAY ORGANIZATION
Figure 1. FUNCTIONAL BLOCK DIAGRAM
V
V
(=2,048 Blocks)
CC
SS
64K Pages
NOTE : Column Address : Starting Address of the Register.
CE
RE
WE
2nd Cycle
3rd Cycle
1st Cycle
Command
A
A
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A
* The device ignores any additional input of address cycles than reguired.
9
0
- A
8
- A
1st half Page Register
(=256 Bytes)
is set to "Low" or "High" by the 00h or 01h Command.
24
7
I/O 0
A
A
A
17
0
9
& High Voltage
CLE ALE
Control Logic
Page Register
512Byte
512 Byte
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Command
Generator
Register
I/O 1
A
A
A
10
18
1
2nd half Page Register
(=256 Bytes)
A
8
WP
I/O 2
A
A
A
11
19
2
16 Byte
16 Byte
I/O 3
A
A
A
12
20
3
3
I/O 4
A
A
A
13
21
I/O 0 ~ I/O 7
4
Global Buffers
(512 + 16)Byte x 65536
Page Register & S/A
I/O Buffers & Latches
I/O 5
A
A
A
256M + 8M Bit
14
22
NAND Flash
5
8 bit
Y-Gating
ARRAY
1 Block =32 Pages
= (16K + 512) Byte
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
1 Device = 528Bytes x 32Pages x 2048 Blocks
I/O 6
A
A
A
15
23
6
= (16K + 512) Byte
= 264 Mbits
I/O 7
A
A
A
FLASH MEMORY
16
24
7
Output
Driver
Column Address
Row Address
(Page Address)
V
V
CC
SS
I/0 0
I/0 7