ta1318afg TOSHIBA Semiconductor CORPORATION, ta1318afg Datasheet - Page 14

• Manufacturer Part Number: ta1318afg
• Description: Sync Processor, Frequency Counter Ic For Tv Component Signals
• Manufacturer: TOSHIBA Semiconductor CORPORATION

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TEST (Test mode)
HD1-INV (HD1 output polarity switch)
HD2-INV (HD2 output polarity switch)
V-FREQUENCY (Vertical frequency switch (pull-in range))
CLP PHS (Clamp pulse phase switch)
FREQ DET SW (Horizontal/vertical frequency counter switch)
INPUT SW (Input signal switch for synchronization)
HD PHASE (HD phase adjustment)
VD1-INV (VD1 output polarity switch)
VD2-INV (VD2 output polarity switch)
Switches DAC1, 2, and 3 outputs. Also used to test IC for shipping.
*(0): DAC outputs are used as DAC.
Switches HD1 output (pin 16) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
Switches HD1 output (pin 19) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
Sets vertical frequency pull-in range, VD-STOP, or free-running frequency.
Free-running frequency is controlled by H-FREQUENCY.
Switches clamp pulse phase.
If no signal input, 0.9 µs pulse is output from the H-C/D circuit.
Switches input signal used for horizontal/vertical frequency counter. This switch is controlled
independently from INPUT SW. The detection result is output as read BUS data.
Switches input signal used for synchronization.
Adjusts phase of HD output from the sync circuit. The phase of the adjustment center value is the same
as that of input H-SYNC or input HD. (Note) Synchronized VD width will change, when HD PHASE will
be changed.
Switches VD1 output (pin 28) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
Switches VD2 output (pin 29) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
(1): DAC1 outputs V. SYNC to the frequency counter.
*(0): Normal
*(0): Normal
*(000)
*(0): 1 µs (3.4%) delay following HD stop phase, 0.8 µs (2.7%) pulse
*(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs
*(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs
*(100000) :
*(0): Normal
*(0): Normal
(001)
(010)
(011)
(100)
(101)
(110)
(111)
(1): 0.5 µs (1.7%) delay following HD stop phase, 0.8 µs (2.7%) pulse
(000000) :
(111111) :
DAC2 outputs H. SYNC or C. SYNC to the frequency counter.
DAC3 outputs IC test pulse for shipping.
−5% (H periodically)
0%
5%
Pull-in Range
FREE-RUN
48~1281 H
48~849 H
48~637 H
48~613 H
48~363 H
48~307 H
VP STOP
(1): Inverse
(1): Inverse
(1): Inverse
(1): Inverse
1125P/30 Hz (33.75 kHz)
750P/60 Hz (45 kHz)
Free-running frequency is controlled by H-FREQUENCY.
(00): 262 H (01): 525 H (10): 562 H (11): 750 H
1125I/60 Hz (33.75 kHz)
525P/60 Hz (31.5 kHz)
PAL/SECAM/50 Hz (15.625 kHz)
PAL/SECAM double scan/100 Hz (31.5 kHz)
NTSC/60 Hz (15.734 kHz)
NTSC double scan /120 Hz (31.5 kHz)
VD output is HIGH
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Format/H (V) Frequency
TA1318AFG
2006-02-27