cx28250 Mindspeed Technologies, cx28250 Datasheet

cx28250

Manufacturer Part Number

cx28250

Description

Cx28250 Atm Physical Interface Phy Devices

Manufacturer

Mindspeed Technologies

Datasheet

1.CX28250.pdf (213 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

cx28250-23ES

Manufacturer:

MNDSPEED

Quantity:

5 510

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

cx28250-23ES

Manufacturer:

JST

Quantity:

5 510

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

cx28250-26

Manufacturer:

MARVELL

Quantity:

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

cx28250-26

Manufacturer:

MINDSPEED

Quantity:

745

Current page: 1 of 213
Download datasheet (3Mb)

CX28250

ATM Physical Interface (PHY) Devices

The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL

clock and data recovery (CDR) circuit. This device has optimized SONET framer

functions for mapping ATM cells to SONET payloads for edge switch applications, and

optional enhanced feature sets for ATM-WAN access applications. It provides ATM

Forum-compliant service termination, and maps the 53-byte cells from an ATM switch

fabric or an adaptation layer processor (SAR) into the SONET payload. The CX28250

device is tailored to meet a wide variety of ATM OC-3 applications. These include WAN

terminals, ATM LAN and WAN switches, ATM OC-3 NICs, and Ethernet-ATM uplink

cards.

for a multi-PHY environment. The ATM framer provides G.804 cell processing, with HEC

generation, checking, and alignment operations. It provides a 155 Mbps SONET

termination with all of the counters needed for capturing both SONET and ATM error

events as specified by the ATM Forum. A proprietary protection scheme allows for

near-instantaneous switching between active and stand-by PHYs.

with the ATM Forum’s WIRE definition. Thus, designers can connect directly to either

fiber optic or Cat 5 Physical Media Dependant (PMD) devices. For diagnostics, three

loopback modes are provided: source loopback, line loopback before the ATM

processor, and line loopback at the UTOPIA block. In addition, the CX28250 can

generate BIP-8 errors and insert invalid HECs.

• Compliance with the jitter requirements of Bellcore’s GR-253-CORE.

• Automatic Protection Switching (APS) using the K1/K2 overhead octets and a Bit Error Rate

• Compatible with Mindspeed CX28297 software driver.

• Access to the S1 octet for system timing.

• Data transmission/reception over the Data Link message channels, D1-D3 and D4-D12.

• Two new input pins have been added: InsPthAIS and InsLnAIS. When asserted high, these

• Two new output pins have also been added: LPOut and PFOut. These indicate that an AIS alarm

Functional Block Diagram

Data Sheet

The CX28250 uses an ATM Forum UTOPIA Level 2-compliant host interface designed

The CX28250 uses a Pseudo-Emitter Coupled Logic (PECL) line interface compliant

The CX28250 supports the following:

(BER) integrator.

pins cause the CX28250 to generate an AIS in the appropriate overhead.

has been received.

ATM WIRE

Interface

Line

Recovery

Interface

Clock

PMD

Overhead Processor

SONET Framer and

(GR-253-CORE)

STS-3c/STM-1

Microprocessor Interface

Microprocessor Bus

8 Bits

(G.804 Cell Processing)

Mindspeed Technologies

ATM Formatter

UTOPIA

Level 2

4-cell

FIFO

4-cell

FIFO

CX28250

Host

Interface

UTOPIA

Level 2

Interface

8/16 Bits

™

500035_001

Distinguishing Features

• Tested APS software driver available

• Synthesizes a 155.52 MHz clock

• UTOPIA Level 2 interface

• Meets ITU, ANSI, and ATM Forum

• ATM Forum WIRE interface for PMDs

• D1-D3, D4-D12 external data link

• Supports APS (K1/K2 bytes)

• Line Fail and Path Fail outputs

• SRAM-style microprocessor

• Glueless interface to the CX2823x

• JTAG (IEEE 1149.1a-1993) compliant

• 8 kHz and 19.44 MHz selectable sync

• SONET overhead processing

• Automatic collection of one-second

• Low power consumption-500 mW

• 3.3 V, (–40

• Package: 156-pin BGA

Applications

• Switches, Hubs, Routers

• LAN NIC cards

• DSLAM uplinks

Line Interface

• ATM Forum WIRE interface

• PECL I/O, compatible with PMD

• Clock recovery from NRZ input data

• Recovery of receive-octet alignment

• Select transmit clock from input or

from Mindspeed

from an 19.44 MHz input

standards

using PECL

interface for all control and

configuration registers

segmentation and reassembly

devices

outputs

statistics

specification compliant

optical and UTP interface devices

and octet clock from F6/28 framing

pattern

recovered receive clock

C to 85

28250-DSH-002-C

June 2005

Related parts for cx28250

Related keywords

cx28250 datasheet
cx28250 data sheet
cx28250 pdf datasheet
cx28250 component
cx28250 part
cx28250 distributor
cx28250 RoHS
cx28250 datasheet download