FM24C04C-G RAMTRON [Ramtron International Corporation], FM24C04C-G Datasheet
FM24C04C-G
Related parts for FM24C04C-G
FM24C04C-G Summary of contents
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... Write Protect VSS Ground VDD Supply Voltage Ordering Information “Green”/RoHS 8-pin SOIC FM24C04C-G “Green”/RoHS 8-pin SOIC, FM24C04C-GTR Tape & Reel Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com VDD WP SCL SDA ...
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... Write Protect: When WP is high, the entire array is write-protected. When WP is low, all addresses may be written. This pin is internally pulled down connect VDD Supply Supply Voltage VSS Supply Ground Rev. 1.1 June 2011 Address Latch Figure 1. Block Diagram FM24C04C FRAM Array 8 Data Latch Page ...
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... This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24C04C due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
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... When a read operation is complete and no more data is needed, the receiver must not acknowledge acknowledges the last byte, this will cause the FM24C04C to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command. Slave Address The first byte that the FM24C04C expects after a start condition is the slave address ...
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... After all address information has been transmitted, data transfer between the bus master and the FM24C04C can begin. For a read operation the FM24C04C will place 8 data bits on the bus then wait for an acknowledge. If the acknowledge occurs, the next sequential byte will be transferred. If the acknowledge is not sent, the read operation is concluded ...
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... FM24C04C should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24C04C Rev. 1.1 June 2011 Address & Data 0 A Word Address Acknowledge Figure 5 ...
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... Therefore, endurance cycles are applied for each read or write cycle. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM24C04C, a row is 64 bits wide. Every 8-byte boundary marks Rev. 1.1 June 2011 ...
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... Rev 4.5V to 5.5V unless otherwise specified) DD Min 4 other inputs -0. Stop command issued FM24C04C Ratings -1.0V to +7.0V -1.0V to +7.0V and V < V +1. -55 125C 260 C 3kV 1.25kV 100V MSL-1 Typ Max Units Notes 5.0 5.5 V A 100 ...
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... DD Max Units min 4.5V to 5.5V unless otherwise specified) DD min) DD waveform. DD FM24C04C Max Min Max Units Notes 400 0 1000 kHz s 0.6 s 0.4 s 0.9 0.55 s 0.5 s 0.25 s 0. 100 ns 300 300 ns 1 300 100 ...
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... 0 HIGH 1/fSCL t AA Stop Start t HD:DAT t t SU:DAT HD:STA Stop Start Min FM24C04C Equivalent AC Load Circuit 5.5V 1700 Output 100 LOW t HD:DAT t SU:DAT t DH Acknowledge t AA Acknowledge Max Units Notes - Years - ...
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... Legend: XXXXXX= part number, P= package type XXXXXXX-P R=rev code, LLLLLLL= lot code RLLLLLLL RIC=Ramtron Int’l Corp, YY=year, WW=work week RICYYWW Example: FM24C04C, “Green”/RoHS SOIC package, Year 2010, Work Week 49 FM24C04C-G A00002G1 RIC1049 Rev. 1.1 June 2011 Recommended PCB Footprint 3.90 0.10 6 ...
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... Revision History Revision Date 1.0 5/20/2011 1.1 6/30/2011 Rev. 1.1 June 2011 Summary Initial Release Added ESD ratings. FM24C04C Page ...