FM24CL64_07 RAMTRON [Ramtron International Corporation], FM24CL64_07 Datasheet
FM24CL64_07
Related parts for FM24CL64_07
FM24CL64_07 Summary of contents
Page 1
FM24CL64 64Kb Serial 3V FRAM Memory Features 64K bit Ferroelectric Nonvolatile RAM Organized as 8,192 x 8 bits Unlimited Read/Write Cycles 45 year Data Retention NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface MHz maximum ...
Page 2
Counter ` SDA Serial to Parallel SCL WP Control Logic A0-A2 Pin Description Pin Name Type Pin Description A0-A2 Input Address 0-2. These pins are used to select one devices of the same type on the ...
Page 3
Overview The FM24CL64 is a serial FRAM memory. The memory array is logically organized as a 8,192 x 8 bit memory array and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial ...
Page 4
SCL SDA Stop (Master) (Master) Stop Condition A stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations using the FM24CL64 should end with a stop condition. If ...
Page 5
Device Slave Select R Figure 4. Slave Address Addressing Overview After the FM24CL64 (as receiver) acknowledges the device address, the master can place the memory address ...
Page 6
Start By Master S Slave Address By FM24CL64 Start By Master S Slave Address FM24CL64 Read Operation There are two basic types of read operations. They are current address read and selective address read current ...
Page 7
This simultaneously aborts the write operation and allows the read command to be issued with the device address LSB Start By Master S By FM24CL64 Start Address By Master S Slave Address By FM24CL64 Start ...
Page 8
Electrical Specifications Absolute Maximum Ratings Symbol V Power Supply Voltage with respect Voltage on any pin with respect Storage Temperature STG T Lead Temperature (Soldering, 10 seconds) LEAD V Electrostatic Discharge Voltage ...
Page 9
AC Parameters ( Symbol Parameter f SCL Clock Frequency SCL t Clock Low Period LOW t Clock High Period HIGH t SCL Low to SDA Data Out Valid AA t Bus ...
Page 10
Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are ...
Page 11
Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme Legend: XXXX= part number, P= package type LLLLLLL= lot code XXXXXXX-P RIC=Ramtron Int’l Corp, ...
Page 12
DFN (4.0mm x 4.5mm body, 0.95mm pitch) 4.50 ±0.1 Pin 1 0.75 ±0.05 0.95 Note: All dimensions in millimeters. DFN Package Marking Scheme for Body Size 4.0mm x 4.5mm Legend: RIC=Ramtron Int’l Corp, G=”green” DFN package XXXX=base part number ...
Page 13
Revision History Revision Date 0.1 7/21/00 0.2 5/9/01 0.3 10/11/01 1.0 3/29/02 2.0 7/23/03 2.1 3/17/04 3.0 1/19/05 3.1 3/8/05 Rev. 3.1 Mar. 2005 Summary Initial Release Endurance changed to unlimited. Changed Data Retention table. Added pin numbers to pinout. ...