FM24CL16B-DG RAMTRON [Ramtron International Corporation], FM24CL16B-DG Datasheet - Page 6

• Manufacturer Part Number: FM24CL16B-DG
• Description: 16Kb Serial 3V F-RAM Memory
• Manufacturer: RAMTRON [Ramtron International Corporation]

Read Operation
There are two types of read operations. They are
current address read and selective address read. In a
current address read, the FM24CL16B uses the
internal address latch to supply the lower 8 address
bits. In a selective read, the user performs a procedure
to set these lower address bits to a specific value.
Current Address & Sequential Read
As mentioned above the FM24CL16B uses an
internal latch to supply the lower 8 address bits for a
read operation. A current address read uses the
existing value in the address latch as a starting place
for the read operation. This is the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. The 3
page select bits in the slave ID specify the block of
memory that is used for the read operation. On the
next clock, the FM24CL16B will begin shifting out
data from the current address. The current address is
the 3 bits from the slave ID combined with the 8 bits
that were in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte, the internal address counter
will be incremented. Each time the bus master
acknowledges a byte this indicates that the
FM24CL16B should read out the next sequential
byte.
Rev. 1.4
Feb. 2011
By FM24CL16
By FM24CL16
By Master
By Master
Start
S
Start
S
Slave Address
Slave Address
0
A
Figure 6. Multiple Byte Write
0
Figure 5. Single Byte Write
Address & Data
Word Address
A
Address & Data
Word Address
A
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most likely create a bus contention as the
FM24CL16B attempts to read out additional data
onto the bus. The four valid methods are as follows.
1.
2.
3.
4.
If the internal address reaches 7FFh it will wrap
around to 000h on the next read cycle. Figures 7 and
8 show the proper operation for current address reads.
Selective (Random) Read
A simple technique allows a user to select a random
address location as the starting point for a read
operation. It uses the first two bytes of a write
operation to set the internal address byte followed by
subsequent read operations.
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol, the
bus master then sends the word address byte that is
loaded into the internal address latch. After the
FM24CL16B acknowledges the word address, the
bus
Acknowledge
The bus master issues a no-acknowledge in the
9
This is illustrated in the diagrams below. This is
the preferred method.
The bus master issues a no-acknowledge in the
9
The bus master issues a stop in the 9
cycle. Bus contention may result.
The bus master issues a start in the 9
cycle. Bus contention may result.
th
th
Data Byte
Acknowledge
master
clock cycle and a start in the 10
clock cycle and a stop in the 10
A
FM24CL16B - 16Kb 3V I2C F-RAM
issues
Data Byte
A
a
Data Byte
start
A
Stop
condition.
P
th
th
.
clock cycle.
A
Page 6 of 13
Stop
P
th
th
clock
clock
This