IDT7026L IDT [Integrated Device Technology], IDT7026L Datasheet - Page 10

• Manufacturer Part Number: IDT7026L
• Description: HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
NOTES:
1. R/
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
6. Timing depends on which enable signal is asserted last,
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 200mV from steady state with the Output
8. If
9. To access RAM,
ADDRESS
CE
Test Load (Figure 2).
to be placed on the bus for the required t
be as short as the specified t
ADDRESS
DATA
WR
UB
DATA
CE
OE
UB
W
DATA
or
is measured from the earlier of
or
or
is LOW during R/
or
CE
SEM
or
R/
OUT
CE
R/
OE
LB
IN
SEM
or
W
IN
LB
W
or
SEM
(9)
(9)
(9)
UB
(9)
LOW transition occurs simultaneously with or after the R/
CE
and
= V
LB
W
IL
controlled write cycle, the write pulse width must be the larger of t
must be HIGH during all address transitions.
and
WP
t
AS
SEM
t
.
AS
(6)
EW
(6)
CE
= V
or t
(4)
or R/
IH
DW
. To access semaphore,
WP
. If
W
) of a LOW
OE
(or
SEM
is HIGH during an R/
t
WZ
or R/
(7)
CE
t
CE
AW
t
AW
t
WC
and a LOW R/
t
W
or R/
WC
) going HIGH to the end of write cycle.
t
t
WP
EW
W
CE
.
(2)
(2)
= V
W
6.17
CE CE CE CE CE
controlled write cycle, this requirement does not apply and the write pulse can
IH
W
W
W W W W W
,
and
for memory array writing cycle.
LOW transition, the outputs remain in the High-impedance state.
UB UB
UB UB
UB
CONTROLLED TIMING
t
SEM
DW
t
DW
,
LB LB LB LB LB
= V
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IL
CONTROLLED TIMING
WP
. t
t
EW
or (t
WR
must be met for either condition.
(3)
WZ
t
t
DH
+ t
t
WR
DH
t
DW
OW
(3)
) to allow the I/O drivers to turn off and data
(1,5,8)
t
HZ
(7)
(4)
(1,5)
2939 drw 08
2939 drw 09
10