IDT7026L IDT [Integrated Device Technology], IDT7026L Datasheet - Page 15

• Manufacturer Part Number: IDT7026L
• Description: HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION
NOTES:
1. Pins
2. LOW if the inputs to the opposite port were stable prior to the address and
3. Writes to the left port are internally ignored when
FUNCTIONAL DESCRIPTION
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7026 has an
automatic power down feature controlled by
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(
memory array is permitted.
BUSY LOGIC
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/
pin operates solely as a write inhibit input pin. Normal opera-
tion can be programmed by tying the
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port LOW.
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
CE
CE CE CE CE CE
X
H
X
L
a master. Both are inputs when configured as a slave.
the IDT7026 are push pull, not open drain outputs. On slaves the
input internally inhibits writes.
enable inputs of this port. HIGH if the inputs to the opposite port became
stable after the address and enable inputs of this port. If t
either
cannot be LOW simultaneously.
driving LOW regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
less of actual logic level on the pin.
The IDT7026 provides two ports with separate control,
Busy Logic provides a hardware indication that both ports
The use of busy logic is not required or desirable for all
The busy outputs on the IDT 7026 RAM in master mode,
L
HIGH). When a port is enabled, access to the entire
BUSY
BUSY
CE CE CE CE CE
H
X
X
L
Inputs
R
L
L
and
NO MATCH
or
A
A
MATCH
MATCH
MATCH
0R
BUSY
0L
BUSY
-A
-A
13L
13R
R
R
are both outputs when the part is configured as
= LOW will result.
S
BUSY
BUSY
BUSY
BUSY
BUSY
pin. Once in slave mode the
BUSY
(2)
H
H
H
L
Outputs
(1)
R
outputs are driving LOW regard-
BUSY
BUSY
BUSY
BUSY
BUSY
BUSY
(2)
H
H
H
BUSY
R
(1)
L
and
BUSY
BUSY
Normal
Normal
Normal
Write Inhibit
pins HIGH. If
CE
BUSY
APS
Function
L
. The
X
outputs are
outputs on
is not met,
R
2683 tbl 17
outputs
BUSY
BUSY
CE
(3)
X
6.17
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7026 RAM the busy pin is
an output if the part is used as a master (M/
busy pin is an input if the part used as a slave (M/
shown in Figure 3.
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with either the R/
to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.
SEMAPHORES
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer’s software. As an example, the sema-
phore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
BUSY
When expanding an IDT7026 RAM array in width while
If two or more master parts were used when expanding in
The busy arbitration, on a master, is based on the chip
The IDT7026 is an extremely fast Dual-Port 16K x 16
The Dual-Port RAM features a fast access time, and both
Figure 3. Busy and chip enable routing for both width and depth
L
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MASTER
Dual Port
RAM
BUSY
MASTER
Dual Port
RAM
BUSY
L
L
expansion with IDT7026 RAMs.
BUSY
BUSY
CE
CE
W
R
R
signal or the byte enables. Failure
SLAVE
Dual Port
RAM
BUSY
SLAVE
Dual Port
RAM
BUSY
L
L
BUSY
BUSY
S
CE
CE
pin = H), and the
R
R
S
pin = L) as
BUSY
2939 drw 16
R
15