IDT70V3589 IDT [Integrated Device Technology], IDT70V3589 Datasheet - Page 2

• Manufacturer Part Number: IDT70V3589
• Description: HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
• Manufacturer: IDT [Integrated Device Technology]

Description:
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3599/89 has been optimized for applications having unidirectional
Pin Configuration
NOTES:
1. A
2. All V
3. All V
4. All V
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
set to V
The IDT70V3599/89 is a high-speed 128/64K x 36 bit synchronous
16
is a NC for IDT70V3589.
DDQ
DD
SS
IL
pins must be connected to ground supply.
pins must be connected to 3.3V power supply.
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
(0V).
06/28/02
C1
E1
F1
K1
R1
T1
U1
B1
V
D1
G1
H1
J1
L1
M1
N1
P1
I/O
A1
V
V
I/O
I/O
I/O
I/O
I/O
V
I/O
I/O
IO
I/O
V
V
V
DDQL
DDQL
DDQL
DDQL
SS
DD
SS
19L
33R
20R
28R
29R
32R
22L
23L
31L
26L
R2
U2
D2
E2
F2
H2
K2
L2
N2
P2
T2
A2
B2
C2
I/O
I/O
G2
J2
M2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO
V
V
V
V
V
V
SS
SS
SS
DD
SS
SS
18L
23R
19R
22R
26R
33L
35L
32L
28L
29L
34L
E3
P3
R3
U3
B3
C3
V
D3
F3
K3
N3
T3
PL/ FT
V
G3
H3
J3
L3
M3
V
A3
I/O
I/O
I/O
V
I/O
V
I/O
I/O
I/O
V
(1,2,3,4,5)
I/O
V
DDQR
V
DDQR
DDQR
DDQR
DDQR
DDQL
SS
SS
18R
31R
21L
24L
27R
30R
34R
25L
R
B4
C4
D4
E4
F4
G4
I/O
H4
J4
K4
L4
M4
N4
P4
R4
T4
U4
PL/ FT
I/O
A4
I/O
I/O
I/O
I/O
TDO
I/O
TMS
TCK
TDI
V
V
V
V
NC
SS
24R
SS
SS
SS
25R
21R
27L
35R
20L
30L
L
P5
R5
T5
B5
C5
D5
U5
TRST
A5
A
A
NC
NC
NC
NC
NC
15L
15R
R6
B6
C6
D6
P6
U6
T6
A6
A
A
A
A
A
A
A
A
16L
16R
13L
14L
13R
11R
11L
14R
(1)
(1)
C7
P7
R7
U7
A7
B7
D7
T7
A
A
A
A
A
A
A
A
10L
12R
10R
12L
9R
9L
7L
7R
70V3599/89BF
208-Pin fpBGA
P8
R8
T8
U8
B8
C8
D8
A8
BE
BE
BE
BE
BE
BE
A
A
Top View
6.42
8L
8R
BF-208
2L
0L
2R
3R
0R
3L
2
or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE
enter a very low standby power mode.
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (V
B9
P9
R9
A9
T9
U9
C9
D9
CE
BE
CE
BE
CE
CE
V
V
DD
DD
The 70V3599/89 can support an operating voltage of either 3.3V or
1R
1L
0R
1L
0L
1R
(6)
B10
C10
D10
P10
A10
R10
T10
U10
OE
(7)
V
V
V
V
V
OE
V
DD
SS
SS
DD
SS
SS
L
R
D11
P11
R11
A11
B11
C11
REPEAT
T11
ADS
CLK
ADS
R/W
CLK
R/W
0
Industrial and Commercial Temperature Ranges
and CE
L
L
R
R
IH
L
R
L
R12
U12
A12
D12
P12
CNTEN
T12
(3.3V), and 2.5V if OPT pin for that port is
CNTEN
B12
C12
A
A
A
A
A
A
5R
3R
5L
6L
3L
6R
1,
L
R
P13
R13
U13
B13
C13
D13
T13
DD
A13
permits the on-chip circuitry of each port to
V
A
A
A
A
A
A
A
DD
4R
1R
2R
0R
4L
2L
) remains at 3.3V.
1L
L14
N14
C14
D14
F14
G14
J14
K14
M14
R14
T14
U14
B14
E14
H14
P14
A14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
V
V
V
V
V
V
A
SS
DD
DD
SS
0L
SS
SS
SS
SS
DD
17R
12L
6R
3R
7R
9L
2L
B15
C15
G15
N15
P15
R15
A15
D15
E15
F15
V
H15
J15
K15
L15
M15
T15
U15
V
I/O
V
I/O
V
V
OPT
I/O
V
OPT
I/O
I/O
IO
I/O
I/O
V
DDQR
DDQL
DDQL
DDQL
DDQL
DDQL
DD
16R
13R
12R
9R
7L
6L
3L
0R
L
R
A16
B16
C16
D16
E16
F16
G16
H16
J16
K16
L16
M16
N16
P16
R16
T16
U16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
10L
17L
16L
15L
14L
11L
8R
4R
5R
1R
0L
5617 drw 02c
C17
F17
G17
L17
M17
P17
R17
A17
B17
D17
E17
V
H17
J17
V
K17
V
N17
V
T17
U17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
DDQR
DDQR
DDQR
DDQR
SS
SS
SS
11R
13L
10R
15R
14R
8L
4L
2R
1L
5L
,