IDT71028S15Y IDT [Integrated Device Technology], IDT71028S15Y Datasheet - Page 6

• Manufacturer Part Number: IDT71028S15Y
• Description: CMOS STATIC RAM 1 MEG (256K x 4-BIT)
• Manufacturer: IDT [Integrated Device Technology]

IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO.1 (
TIMING WAVEFORM OF WRITE CYCLE NO.2 (
NOTES:
1.
2. A write occurs during the overlap of a LOW
3.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
6. Transition is measured 200mV from steady state.
ADDRESS
WE
OE
off and data to be placed on the bus for the required t
minimum write pulse is as short as the specified t
ADDRESS
DATA
DATA
is continuously HIGH. If during a
DATA
or
CS
WE
CS
CS
OUT
IN
WE
LOW transition occurs simultaneously with or after the
CS
must be HIGH during all address transitions.
IN
t
AS
t
(4)
AS
WE
controlled write cycle
CS
and a LOW
WP
.
t
DW
WHZ
. If
(6)
WE
OE
t
t
AW
OE
AW
.
is HIGH during a
WE
is LOW, t
LOW transition, the outputs remain in a high-impedance state.
t
t
t
WP
WC
CW
t
WE
WE
CS
CS
WC
9.4
HIGH IMPEDANCE
(3)
WP
CONTROLLED TIMING)
CONTROLLED TIMING)
must be greater than or equal to t
WE
t
controlled write cycle, this requirement does not apply and the
t
DW
DATA
DW
DATA
IN
VALID
IN
VALID
t
DH
t
t
t
WR
OW
WR
COMMERCIAL TEMPERATURE RANGE
(6)
t
DH
WHZ
(1,2,5)
(1,2,3,5)
+ t
DW
to allow the I/O drivers to turn
t
(4)
CHZ
(6)
2966 drw 08
2966 drw 07
6