IDT71321LA IDT [Integrated Device Technology], IDT71321LA Datasheet - Page 10

• Manufacturer Part Number: IDT71321LA
• Description: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
• Manufacturer: IDT [Integrated Device Technology]

Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
3. t
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
ADDRESS
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
ADDRESS
(Figure 2).
bus for the required t
DATA
WR
DATA
DATA
is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
R/W
CE
R/W
IN
OUT
OE
CE
IN
DW
. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
EW
t
t
AS
or t
AS
(6)
WP
(6)
) of CE = V
(4)
IL
and R/W = V
t
WZ
(7)
t
AW
IL
t
AW
.
t
WC
t
t
WC
WP
t
EW
10
(2)
(2)
t
DW
WP
Military, Industrial and Commercial Temperature Ranges
or (t
t
DW
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be placed on the
t
WR
(3)
t
WR
t
DH
(3)
t
OW
t
DH
t
HZ
(1,5)
(7)
t
HZ
(1,5,8)
(4)
(7)
2692 drw 09
2692 drw 10
WP
.