IDT7203 IDT [Integrated Device Technology], IDT7203 Datasheet - Page 6

• Manufacturer Part Number: IDT7203
• Description: CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
• Manufacturer: IDT [Integrated Device Technology]

CAPACITANCE
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
AC TEST CONDITIONS
NOTES:
1. This parameter is sampled and not 100% tested.
2. With output deselected.
SIGNAL DESCRIPTIONS
Inputs:
DATA IN (D
Controls:
(
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take place.
Both the Read Enable (
be in the HIGH state during the window shown in Figure 2
(i.e. t
change until t
edge of this input if the Full Flag (
hold times must be adhered-to, with respect to the rising edge
of the Write Enable (
sequentially and independently of any on-going read operation.
next write operation, the Half-Full Flag (
and will remain set until the difference between the write pointer
and read pointer is less-than or equal to one-half of the total
memory of the device. The Half-Full Flag (
rising edge of the read operation.
the falling edge of the last write signal, which inhibits further write
operations. Upon the completion of a valid read operation, the
Full Flag (
to begin. When the FIFO is full, the internal write pointer is
blocked from
when it is full.
RS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
Symbol
C
C
IN
OUT
RESET (
WRITE ENABLE (
After half of the memory is filled, and at the falling edge of the
To prevent data overflow, the Full Flag (
) input is taken to a LOW state. During reset, both internal
(1)
RSS
(1,2)
FF
before the rising edge of
Output Capacitance
RS
RS
0
) will go HIGH after t
Input Capacitance
W
–D
) — Reset is accomplished whenever the Reset
RSR
, so external changes in
Parameter
8
) — Data inputs for 9-bit wide data.
after the rising edge of
(1)
W
W
W
(T
) — A write cycle is initiated on the falling
R
R
). Data is stored in the RAM array
) and Write Enable (
A
= +25 C, f = 1.0 MHz)
RFF
FF
Condition
V
V
) is not set. Data set-up and
OUT
, allowing a new valid write
IN
W
= 0V
HF
= 0V
RS
RS
GND to 3.0V
See Figure 1
will not affect the FIFO
) will be set to LOW,
) and should not
FF
HF
1.5V
1.5V
RS
5ns
RS
) will go LOW on
W
W
) is reset by the
.
) inputs must
Max.
10
10
2661
2661
Unit
pF
pF
t
t
bl 08
bl 07
5.04
edge of the Read Enable (
set. The data is accessed on a First-In/First-Out basis, inde-
pendent of any ongoing write operations. After Read Enable (
goes HIGH, the Data Outputs (Q
high-impedance condition until the next Read operation. When
all the data has been read from the FIFO, the Empty Flag (
will go LOW, allowing the “final” read cycle but inhibiting further
read operations, with the data outputs remaining in a high-
impedance state. Once a valid write operation has been accom-
plished, the Empty Flag (
Read can then begin. When the FIFO is empty, the internal read
pointer is blocked from
FIFO when it is empty.
purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first device loaded (see
Operating Modes). The Single Device Mode is initiated by
grounding the Expansion In (
data when the Retransmit Enable Control (
LOW. A retransmit operation will set the internal read pointer to
the first location and will not affect the write pointer. The status
of the Flags will change depending on the relative locations of
the read and write pointers. Read Enable (
(
useful when less than 2048/4096/8192/16384 writes are per-
formed between resets. The retransmit feature is not compat-
ible with the Depth Expansion Mode.
Expansion In (
single device mode. Expansion In (
sion Out (
Daisy-Chain Mode.
W
) must be in the HIGH state during retransmit. This feature is
READ ENABLE (
FIRST LOAD/RETRANSMIT (
The IDT7203/7204/7205/7206 can be made to retransmit
EXPANSION IN (
XO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
D.U.T.
) of the previous device in the Depth Expansion or
XI
*Includes jig and scope capacitances.
) is grounded to indicate an operation in the
680
R
R
OR EQUIVALENT CIRCUIT
Figure 1. Output Load
XI
XI
) — A read cycle is initiated on the falling
R
) — This input is a dual-purpose pin.
EF
so external changes will not affect the
R
), provided the Empty Flag (
) will go HIGH after t
XI
).
5V
0
FL
FL
through Q
1.1K
XI
30pF*
/
) is connected to Expan-
RT
RT
) — This is a dual-
R
RT
) and Write Enable
2661 drw 03
8
) input is pulsed
) will return to a
WEF
and a valid
EF
) is not
6
EF
R
)
)