IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 11

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
change in level will only be noticeable if
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.
read operations may begin starting with the first location in
memory. Since IDT Standard mode is selected, every word
read including the first word following Retransmit setup re-
quires a LOW on
Figure 11, Retransmit Timing (IDT Standard Mode) , for the
relevant timing diagram.
of the Retransmit setup by setting
period, the internal read pointer is set to the first location of the
RAM array.
same time, the contents of the first location appear on the
When
If FWFT mode is selected, the FIFO will mark the beginning
When
OR
EF
goes HIGH, Retransmit setup is complete and
goes LOW, Retransmit setup is complete; at the
REN
to enable the rising edge of RCLK. See
OR
EF
HIGH. During this
was HIGH before
outputs. Since FWFT mode is selected, the first word
appears on the outputs, no LOW on
Reading all subsequent words requires a LOW on
enable the rising edge of RCLK. See Figure 12, Retransmit
Timing (FWFT Mode) , for the relevant timing diagram.
of the
RCLK that
on the second rising edge of RCLK after
flag will be updated.
edge of RCLK that
synchronized to WCLK, thus the second rising edge of
WCLK that occurs t
RT
For either IDT Standard mode or FWFT mode, updating
is setup will update
PAE
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
,
RT
HF
is setup.
and
SKEW
PAF
RT
HF
PAF
PAE
is setup will update
flags begin with the rising edge of
after the rising edge of RCLK that
is asynchronous, thus the rising
.
is synchronized to RCLK, thus
RT
is synchronized to RCLK.
RT
REN
is setup, the
is necessary.
HF
.
REN
PAF
PAE
11
to
is