lc72134m Sanyo Semiconductor Corporation, lc72134m Datasheet - Page 12

• Manufacturer Part Number: lc72134m
• Description: Dual Pll Frequency Synthesizer For Fm Tuner Systems
• Manufacturer: Sanyo Semiconductor Corporation

Continued from preceding page.
No.
6
7
8
9
DO pin control data
Phase comparator
Control block/data
Clock time base
Unlocked state
detection data
control data
UL0, UL1
DZ0, DZ1
DOC0
DOC1
DOC2
TBC
• Determines the DO pin output.
• Selects the width of the phase error (øE) detected for PLL lock state discrimination. A phase error is
* When the PLL is unlocked, the DO pin goes low and UL in the serial data output is set to 0.
• Controls the phase comparator dead zone
• Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from the
The open state is selected after a power on reset.
*1. end-UC: IF counter measurement end check
recognized if a phase error in excess of the detection width occurs.
When the PLL is locked, the DO pin goes high and UL in the serial data output is set to 1.
Dead zone width: DZA < DZB < DZC < DZD
BO1 pin. (The BO1 data will be ignored.)
(1) When end-UC is selected and an IF count is started (by switching CTE from 0 to 1), the DO pin
(2) When the IF counter measurement period completes, the DO pin goes to the low level, allowing
(3) The DO pin is set to the open state by performing a serial data input or output operation (when the
*2. Valid when the IFIN2/I1 pin is set to the input port state (L/I1 = 0).
*3. Goes to the open state when the IO pin is set to the output state.
Note: During the data input period (the period that CE is high in IN1, IN2, or IN3 mode), the DO pin goes
DOC2
DZ1
UL1
automatically goes to the open state.
applications to test for the completion of the count period.
CE pin is set high).
(The DO pin will go to the open state if L/I1 is set to 1.)
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
to the open state regardless of the DO pin control data (DOC0 to DOC2). During the data output
period (the period that CE is high in OUT mode) the DO pin state reflects the internal DO serial
data in synchronization with the CL clock, regardless of the DO pin control data (DOC0 to DOC2).
DOC1
UL0
DZ0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
øE detection width
DOC0
Dead band mode
0
1
0
1
0
1
0
1
Stopped
±0.55 µs
±1.11 µs
DZA
DZB
DZC
DZD
0
Low when the PLL is unlocked
LC72134M
end-UC (See *1 below.)
IFIN2/I1 pin state (*2)
The IO2 pin state (*3)
DO pin state
Function
øE is extended by 1 to 2 ms
øE is extended by 1 to 2 ms
Open
Open
Open
Open
øE is output directly
Detection output
Open
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Related data
No. 5814-12/27
UL0, UL1
ULa, ULb
DOC0
DOC1
DOC2
IOC2
CTE
BO1
L/I1