74HC132D,653 NXP Semiconductors, 74HC132D,653 Datasheet - Page 10

• Manufacturer Part Number: 74HC132D,653
• Description: IC TRIGGER NAND QUAD 2IN 14SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC132D,653

• Number Of Circuits: 4
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Logic Type: NAND Gate - Schmitt Trigger
• Number Of Inputs: 2
• Current - Output High, Low: 7.8mA, 7.8mA
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: NAND
• Logic Family: HC
• High Level Output Current: - 5.2 mA
• Low Level Output Current: 5.2 mA
• Propagation Delay Time: 11 ns
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Logical Function: NAND
• Number Of Elements: 4
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 125C
• Package Type: SO
• Number Of Outputs: 1
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 14
• Operating Temperature Classification: Automotive
• Quiescent Current: 2uA
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 2V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1394-2; 74HC132D-T; 933714130653

Philips Semiconductors
HC TYPES
AC waveforms 74HC
AC waveforms 74HC
March 1988
handbook, full pagewidth
HCMOS family characteristics
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET
(2) For AC measurements: t
Fig.4
and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals
are specified in the individual device data sheet.
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
OUTPUT
PRESET
CLOCK
RESET,
INPUT
INPUT
INPUT
r
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
INPUT
OUTPUT
10 %
50%
t su
t rem
50%
t r
10%
50%
t PLH
90%
t PHL
t THL
t WH
10%
max
90%
50%
90%
t h
, there is no constraint on t
t r
1/f max
t TLH
50%
90%
t f
50%
10%
10
t WL
t su
t f
t PHL
t PLH
t TLH
r
, t
f
with 50% duty factor.
MGK564
t h
FAMILY SPECIFICATIONS
t THL
V CC
GND
MGK569
V CC
GND
V CC
GND
V CC
GND