cxd2548r Sony Electronics, cxd2548r Datasheet - Page 39

• Manufacturer Part Number: cxd2548r
• Description: Cd Digital Signal Processor With Built-in Digital Servo And Dac
• Manufacturer: Sony Electronics

PER0 to 7
R0 to R7
L0 to L7,
VF0 to 7
C1F1
ALOCK
XRAOF
EMPH
WFCK
SCOR
GTOP
Signal
LOCK
SPOA
RFCK
FOX
GFS
0
1
1
Command bit
CPUSR = 1
CPUSR = 0
C1F2
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
Focus OK
High when the frame sync and the insertion protection timing match.
GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight
consecutive samples, a low signal is output.
High when the playback disc has emphasis.
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is
output. If GFS is low eight consecutive samples, a low signal is output.
Used during CAV-W mode. Disc rotational speed measurement results. (See Timing Chart
2-3.) VF0 = LSB, VF7 = MSB.
SPOA pin input
Write frame clock output
High when either subcode sync S0 or S1 is detected.
High when the sync protection window is open.
Read frame clock output
Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.
Peak meter register output. Lch L0 to 7 and Rch R0 to 7 peak data. L0 and R0 are LSB.
0
0
1
No Error
Single Error Correction
Irretrievable Error
C1 correction status
XLON pin is high.
XLON pin is low.
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Description
Processing
C2F1
0
1
1
C2F2
0
0
1
No Error
Single Error Correction
Irretrievable Error
C2 correction status
CXD2548R