cxd2548r Sony Electronics, cxd2548r Datasheet - Page 68

• Manufacturer Part Number: cxd2548r
• Description: Cd Digital Signal Processor With Built-in Digital Servo And Dac
• Manufacturer: Sony Electronics

3-8. Channel Clock Regeneration by the Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
The block diagram of this PLL is shown in Fig. 3-10.
The CXD2548R has a built-in three-stage PLL.
• The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary;
• The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock.
• A new digital PLL has been provided for CLV-W mode to follow the rotational speed of the disc in addition
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a
result, T, that is the channel clock, is necessary.
In an actual player, a PLL is necessary to regenerate the channel clock because the fluctuation in the
spindle rotation alters the width of the EFM signal pulses.
when not using the internal VCO2, external LPF and VCO are necessary.
The output of this first-stage PLL is used as a reference for all clocks within the LSI.
to the conventional secondary loop.
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CXD2548R