cxd2548r Sony Electronics, cxd2548r Datasheet - Page 40

• Manufacturer Part Number: cxd2548r
• Description: Cd Digital Signal Processor With Built-in Digital Servo And Dac
• Manufacturer: Sony Electronics

CXD2548R
Peak Meter
XLAT
SQCK
SQSO
L0
L1
L2
L3
L4
L5
L6
L7
R0
R1
R2
R3
R4
R5
R6
R7
(Peak meter)
Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively,
results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data
values (absolute value, upper 8 bits) for Lch and Rch can be read from SQSO by inputting 16 clocks to SQCK.
Peak detection is not performed during SQCK input, and the peak register does not change during readout.
This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270µs to
400µs. The time during which SQCK input is high should be 270 µs or less. Also, peak detection is restarted
270µs to 400µs after SQCK input.
The peak detection register is reset with each readout (16 clocks input to SQCK).
The maximum value during peak detection mode is detected and held in this status until the next readout.
When switching to peak detection mode, readout should be performed one time initially to reset the peak
detection register.
Peak detection can also be performed for previous value hold and average value interpolation data.
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