m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet
m5m4v4s40ctp-12
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m5m4v4s40ctp-12 Summary of contents
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... Auto precharge / All bank precharge controlled Auto and self refresh - 1024 refresh cycles /16.4ms - LVTTL Interface - 400-mil, 50-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch Frequency M5M4V4S40CTP-12 83MHz M5M4V4S40CTP-15 67MHz M5M4V4S40CTP-12, -15 CLK CKE /CS /RAS /CAS /WE DQ0-15 DQMU DQML A0-8 ...
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... BLOCK DIAGRAM Memory Array Bank #0 Mode Register Address Buffer A0-8 BA Type Designation Code M5M4V4S40CTP-12, -15 DQ0-15 I/O Buffer Memory Array Bank #1 Control Circuitry Control Signal Buffer Clock Buffer /CS /RAS /CAS /WE CLK CKE These rules are only applied to the Synchronous DRAM family. ...
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... Vdd, Vss Power Supply VddQ, VssQ Power Supply M5M4V4S40CTP-12, -15 Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls the internal clock. When CKE is low, the internal clock for the following cycle is disabled. CKE is also used to select auto and self refresh ...
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... when PRE is issued both banks are automatically precharged (PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] The REFA command starts an auto-refresh cycle. The refresh address, including the bank address, is generated internally. After this command, the banks are precharged automatically. M5M4V4S40CTP-12, -15 Chip Select : L=select, H=deselect Command Command ...
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... READA Precharge Auto-Refresh REFA Self-Refresh Entry REFS Self-Refresh Exit REFSX Burst Terminate TBST Mode Register Set MRS H=High Level, L=Low Level, V=Valid, X=Don’t Care, n=CLK cycle number NOTE =0, A0-A6 =Mode Address M5M4V4S40CTP-12, -15 CKE CKE /CS /RAS /CAS n ...
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... READ M5M4V4S40CTP-12, -15 /WE Address Command DESEL BA, CA, A8 READ / WRITE ILLEGAL BA BA, A8 PRE / PREA Op-Code Mode-Add X ...
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... WRITE with AUTO L H PRECHARGE M5M4V4S40CTP-12, -15 ) (continued /WE Address Command DESEL BA, CA, A8 READ / READA WRITE / L L BA, CA, A8 WRITEA BA, A8 PRE / PREA ...
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... WRITE RE- COVERING M5M4V4S40CTP-12, -15 /CAS /WE Address Command BA, CA, A8 READ / WRITE ILLEGAL BA BA, A8 PRE / PREA Op-Code Mode-Add ...
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... ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. M5M4V4S40CTP-12, -15 /WE Address Command X X ...
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... CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. M5M4V4S40CTP-12, -15 /CS /RAS /CAS /WE ...
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... SIMPLIFIED STATE DIAGRAM MODE REGISTER SET SUSPEND TBST(for Full Page) CKEL WRITE SUSPEND CKEH WRITEA CKEL WRITEA SUSPEND CKEH POWER APPLIED POWER ON M5M4V4S40CTP-12, -15 REFS MRS REFA IDLE CKEH CLK ACT CKEL CKEH ROW ACTIVE WRITE READ WRITEA READA READ WRITE WRITE ...
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... After tRSC from an MRS operation, the SDRAM is ready for new commands OPCODE LATENCY MODE Burst read / Burst write OPCODE Burst read / Single write 1 1 M5M4V4S40CTP-12, - LTMODE BT BL /CAS LATENCY BURST 3 LENGTH R R BURST R TYPE ...
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... For BL=1,2,4,8 the output data is tristated (Hi-Z) after the last read. For BL=FP (Full Page) the TBST (Burst Terminate) command must be used to stop the output of data. tRCD CLK Command ACT READ X Y Address M5M4V4S40CTP-12, -15 /CAS Latency Timing (BL=4) READ Burst Length Timing (CL= ...
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... Note: For FP Burst the Burst Type must be set to sequential. M5M4V4S40CTP-12, - Burst Length Internal addresses are determined by Burst Type. Column Addressing / Burst Type Sequential ...
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... Internal precharge start timing depends on /CAS Latency. The next ACT command can be issued after tRP from the precharge (PRE). Note: READA is not allowed for FP burst length operations. The SDRAM must be manually precharged. M5M4V4S40CTP-12, -15 ACT READ ...
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... READ with Auto-Precharge (BL=4, CL=3) CLK Command ACT tRCD A0 READ Auto-Precharge Timing (BL=4) CLK Command ACT CL=3 DQ CL=2 DQ CL=1 DQ M5M4V4S40CTP-12, -15 READ ACT READ PRE Qa0 Qa1 Qa2 /CAS latency Burst Length READ Qa0 Qa1 Qa2 Internal Precharge Begins ...
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... Dual Bank Interleaving WRITE (BL=4) CLK Command ACT A0 WRITE with Auto-Precharge (BL=4) CLK Command ACT A0 M5M4V4S40CTP-12, -15 Write ACT tRCD tRCD Da0 Da1 Da2 Da3 Burst Length Write tRCD Da0 Da1 ...
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... DQ’s should be controlled by using DQMU and DQML to prevent bus contention. The output is disabled two cycles automatically after WRITE assertion. Random column access is allowed. Read Interrupted by Write (BL=4, CL=3) CLK Command Read A0 DQMU DQML Q D M5M4V4S40CTP-12, -15 Read Interrupted by Read (BL=4, CL=3) READ READ READ Qai0 Qaj0 ...
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... CLK. A PRE command disables the data output, depending on the /CAS latency. The figures below show examples of how the output data is terminated with a PRE command. Command Command CL=3 Command Command Command CL=2 Command Command CL=1 Command M5M4V4S40CTP-12, -15 Read Interrupted by Precharge (BL=4) CLK READ DQ Q0 READ PRE DQ Q0 READ PRE DQ ...
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... FP bursts. The figures below show examples, of how the output data is terminated with TBST. CLK Command DQ Command CL=3 DQ Command DQ Command DQ Command CL=2 DQ Command DQ Command DQ CL=1 Command DQ M5M4V4S40CTP-12, -15 Read Interrupted by Burst Terminate (BL=4) READ TBST Q0 Q1 READ TBST Q0 Q1 READ TBST Q0 READ TBST READ TBST Q0 ...
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... WRITE to READ interval is a minimum of one CLK. The input data the interrupting READ cycle is "don’t care". Write Interrupted by Read (BL=4, CL=3) CLK Command Write READ A0 DQMU DQML DQ Dai0 M5M4V4S40CTP-12, -15 Write Write Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Write Qaj0 Qaj1 ...
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... The WRITE to TERM minimum interval is one CLK. Write Interrupted by Burst Terminate (BL=4) CLK Command Write A0 DQMU DQML DQ Dai0 M5M4V4S40CTP-12, -15 PRE ACT tWR tRP This data should be masked to satisfy tWR requirement. TERM Dai1 Dai2 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... Subsequent commands (except NOP or DESELECT) must not be asserted before tRC from the REFA command. Auto-Refresh CLK /CS /RAS /CAS /WE CKE A0-8 BA Auto Refresh on Bank 0 M5M4V4S40CTP-12, -15 NOP or DESLECT minimum tRC MITSUBISHI ELECTRIC MITSUBISHI LSIs Auto Refresh on Bank 1 23 ...
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... Until the tRC time has expired, only DESELor NOP commands may be asserted after an REFSX command. Self-Refresh CLK /CS /RAS /CAS /WE CKE A0-8 BA Self Refresh Entry M5M4V4S40CTP-12, -15 Stable CLK Self Refresh Exit MITSUBISHI ELECTRIC MITSUBISHI LSIs NOP new command X 0 minimum tRC for recovery 24 ...
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... CKE int.CLK CLK CKE Command PRE CKE Command ACT CLK CKE Command Write DQ D0 M5M4V4S40CTP-12, -15 Power Down by CKE Standby Power Down NOP NOP NOP NOP NOP Active Power Down NOP NOP NOP NOP NOP DQ Suspend by CKE READ MITSUBISHI ELECTRIC ...
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... The DQMU and DQML to output “Hi-Z” latency is two, i.e., the output will be “Hi-Z” at the rising edge of second clock after DQM is applied. CLK Command Write DQML DQ(0-7) D0 masked by DQML=High DQMU DQ(8-15 masked by DQMU=High M5M4V4S40CTP-12, -15 DQMU/DQML Function READ disabled by DQMU=High MITSUBISHI ELECTRIC MITSUBISHI LSIs disabled by DQML=High Q0 ...
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... Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Symbol CI(A) Input Capacitance, address pin CI(C) Input Capacitance, control pin CI(K) Input Capacitance, CLK pin CI/O Input Capacitance, I/O pin M5M4V4S40CTP-12, -15 Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ °C Parameter Min. 3 ...
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... Parameter VOH (DC) High-Level Output Voltage (DC) VOL (DC) Low-Level Output Voltage (DC) IOZ Off-state Output Current I Input Current I M5M4V4S40CTP-12, -15 Test Conditions tRC=min, tCLK=min, BL=1, CL=3 both banks idle, tCLK=min, CKE=H both banks idle, tCLK=min, CKE=L both banks active, tCLK=min, CKE=H tCLK=min, BL=4, CL=3, 1 bank idle tRC=min, tCLK=min CKE <0.2v ...
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... Row Active time tRP Row Precharge time tWR Write Recovery time tRRD Act to Act Delay time Mode Register Set tRSC Cycle time tPDE Power Down Exit time tREF Refresh Interval time CLK Signal M5M4V4S40CTP-12, -15 0.8V to 2.0V 1.4V Limits -12 Min. Max. CL=1 30 CL ...
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... Row Access Time Output Hold time from tOH CLK Delay time, output low tOLZ impedance from CLK Delay time, output high tOHZ impedance from CLK Output Load Condition ohm V OUT 50pF CLK DQ M5M4V4S40CTP-12, -15 -12 Min. Max. CL=1 27 CL=2 9.5 CL=3 8 24.5 54 =1.4V CLK V =1 ...
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... SDRAM (Rev. 0.3) Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM WRITE CYCLE (single bank) CLK /CS /RAS tRCD /CAS /WE CKE DQMU DQML A0 ACT M5M4V4S40CTP-12, -15 tRC tRAS Y tWR WRITE PRE MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4 tRP X X ACT 31 ...
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... Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM WRITE CYCLE (dual bank) CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU DQML Xa A0 ACTa WRITEa M5M4V4S40CTP-12, -15 tRC tRAS tRAS tRCD tWR ACTb WRITEb PREa MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... SDRAM (Rev. 0.3) Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM READ CYCLE (single bank) CLK /CS /RAS tRCD /CAS /WE CKE DQMU DQML X A0 ACT M5M4V4S40CTP-12, -15 tRC tRAS tCAC tRAC READ PRE MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4, CL=3 tRP ACT 33 ...
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... Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM READ CYCLE (dual bank) CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU DQML Xa A0 ACTa READa M5M4V4S40CTP-12, -15 tRC tRAS tRAS tRCD tCAC tRAC tRAC ACTb READb PREa MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4, CL=3 ...
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... SDRAM (Rev. 0.3) Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM WRITE to READ (single bank) CLK /CS /RAS tRCD /CAS /WE CKE DQMU DQML A0 ACT M5M4V4S40CTP-12, -15 tRAS WRITE READ MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4, CL tCAC PRE 35 ...
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... Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM WRITE to READ (dual bank) CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU DQML Xa A0 ACTa WRITEa M5M4V4S40CTP-12, -15 tRC tRAS tRAS tRCD tWR tCAC ACTb READb PREa MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4, CL=3 ...
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... Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM DQM Byte control for WRITE to READ (single bank) CLK /CS /RAS tRCD /CAS /WE CKE DQML DQMU A0 (0-7) DQ (8-15) ACT M5M4V4S40CTP-12, -15 tRAS WRITE READ MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4,CL tCAC ...
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... SDRAM (Rev. 0.3) Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM READ to WRITE (single bank) CLK /CS /RAS tRCD /CAS /WE CKE DQMU DQML A0 ACT M5M4V4S40CTP-12, -15 tRAS for output disable tCAC tRAC READ MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4, CL=3 Y tWR WRITE PRE ...
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... Synchronous DRAM READ to WRITE (dual bank) CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU DQMU DQML DQML Xa A0 ACTa M5M4V4S40CTP-12, -15 tRC tRAS tRAS tRCD for output disable tCAC tRAC READa ACTb PREa MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4, CL=3 tRP Y ...
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... WRITE with AUTO-PRECHARGE (WRITEA) CLK /CS /RAS tRCD /CAS /WE CKE DQMU DQML A0 ACT Note: WRITEA should not be used for Full Page (FP) burst operations. M5M4V4S40CTP-12, -15 tRC WRITEA internal precharge starts this timing depends on BL MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4 tWR + tRP X X ACT 40 ...
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... READ with AUTO-PRECHARGE (READA) CLK /CS /RAS tRCD /CAS /WE CKE DQMU DQML A0 ACT Note: READA should not be used for Full Page (FP) burst operations. M5M4V4S40CTP-12, -15 tRC tCAC tRAC READA internal precharge starts this timing depends on BL MITSUBISHI ELECTRIC MITSUBISHI LSIs BL=4, CL=3 tRP ...
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... SDRAM (Rev. 0.3) Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM AUTO-REFRESH CLK /CS tRP /RAS /CAS /WE CKE DQMU DQML A0 PREA if any bank is active, it must be precharged M5M4V4S40CTP-12, -15 tRC REFA MITSUBISHI ELECTRIC MITSUBISHI LSIs REFA 42 ...
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... SDRAM (Rev. 0.3) Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM SELF-REFRESH ENTRY CLK /CS tRP /RAS /CAS /WE CKE DQMU DQML A0 PREA if any bank is active, it must be precharged M5M4V4S40CTP-12, -15 REFS MITSUBISHI ELECTRIC MITSUBISHI LSIs 43 ...
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... SDRAM (Rev. 0.3) Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM SELF-REFRESH EXIT CLK /CS /RAS /CAS /WE CKE DQMU DQML A0 M5M4V4S40CTP-12, -15 NOP or DESEL internal CLK re-start MITSUBISHI ELECTRIC MITSUBISHI LSIs tRC X X ACT 44 ...
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... SDRAM (Rev. 0.3) Feb ‘97 Preliminary 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM MODE REGISTER SET CLK /CS tRP /RAS /CAS /WE CKE DQMU DQML A0 any bank is active, it must be precharged M5M4V4S40CTP-12, -15 BL=4, CL=3 tRSC tRCD mode tRAC MITSUBISHI ELECTRIC MITSUBISHI LSIs tCAC 45 ...