m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 21

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

SDRAM (Rev. 0.3)
[ Write Interrupted by Write ]
access is allowed. WRITE to WRITE interval is a minimum of one CLK.
[ Write Interrupted by Read ]
is allowed. WRITE to READ interval is a minimum of one CLK. The input data on DQ at the interrupting
READ cycle is "don’t care".
Feb ‘97 Preliminary
A burst write operation can be interrupted by a new write to the same or opposite bank. Random column
A burst write operation can be interrupted by a read of the same or opposite bank. Random column access
Command
Command
DQMU
DQML
CLK
A0-7
A8
BA
CLK
A0-7
A8
BA
DQ
DQ
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
Write
Write
Dai0
Dai0
Yi
0
0
Yi
0
0
Write Interrupted by Read (BL=4, CL=3)
Write Interrupted by Write (BL=4)
READ
Write
Daj0
Yj
0
0
Yj
0
0
Daj1
MITSUBISHI ELECTRIC
Write
Dbk0
Yk
0
1
M5M4V4S40CTP-12, -15
Qaj0
Dbk1 Dbk2
Qaj1
Write
Dal0
Yl
0
0
Write
Dak0 Dak1
Dal1
Yk
0
0
Dal2
READ
Dal3
Yl
0
1
MITSUBISHI LSIs
Qbl0
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