m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 3

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m5m4v4s40ctp-12

Manufacturer Part Number
m5m4v4s40ctp-12
Description
2-bank 131072-word 16-bit Synchronous Dram
Manufacturer
Mitsumi Electronics, Corp.
Datasheet

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SDRAM (Rev. 0.3)
PIN FUNCTION
/RAS, /CAS, /WE
Feb ‘97 Preliminary
VddQ, VssQ
Vdd, Vss
DQ0-15
DQMU
DQML
A0-8
CLK
CKE
/CS
BA
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
Power Supply
Power Supply
Input / Output
Input
Input
Input
Input
Input
Input
Input
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
Clock Enable: CKE controls the internal clock. When CKE is low, the
internal clock for the following cycle is disabled. CKE is also used to select
auto and self refresh. After self-refresh mode is started, CKE acts as an
asynchronous input to maintain and exit the mode.
Chip Select: When /CS is high, all commands are inhibited.
/RAS, /CAS, and /WE are used to define basic commands.
A0-8 specify the Row and Column addresses within the selected bank.
The Row Address is set by A0-8 and the Column Address is set by A0-7.
A8 is also used to indicate the precharge option. When A8 is high during
read or write command, an auto precharge is performed. When A8 is
high during a precharge command, both banks are precharged.
Bank Address: BA is not simply A9. BA specifies the bank to which a
command is applied. BA must be set during the ACT, PRE, READ,
and WRITE commands.
Data In and data out are referenced to the rising edge of CLK.
Lower Din(0-7) Mask; Lower Dout(0-7) Disable; When DQML is high
during burst write Din(0-7) for the current cycle is masked. When DQML
is high during burst read Dout(0-7) is disabled two cycles later.
Power Supply for the memory array and peripheral circuitry.
Power Supply for the output buffers only.
Upper Din(8-15) Mask; Upper Dout(8-15) Disable; When DQMU is high
during burst write Din(8-15) for the current cycle is masked. When DQMU
is high during burst read Dout(8-15) is disabled two cycles later.
MITSUBISHI ELECTRIC
M5M4V4S40CTP-12, -15
MITSUBISHI LSIs
3

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