m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 17

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

WRITE
SDRAM beginning on the rising edge of CLK in the same cycle that the WRITE command is applied.
The remaining input data will be clocked in on the subsequent CLK cycles. The number of writes depends
on the BL set in the mode register. The start address is specified by A7-0 and the address sequence is
defined by the Burst Type. A WRITE command may be applied to any active bank. This allows the row
precharge time (tRP) to be hidden behind continuous input data. Write recovery time (tWR) is required
between the last write and subsequent precharge (PRE) inside of a bank.
is input. All commands (READ, WRITE, PRE, ACT) to the same bank are inhibited until the internal
precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT
command can be issued after tRP. WRITEA cannot be used for FP burst length operations.
clocked in when the WRITE command is issued and the remaining burst length is ignored. The read data
burst length is unaffected while in this mode.
SDRAM (Rev. 0.3)
Feb ‘97 Preliminary
A WRITE command can be issued after tRCD from the bank activation (ACT). Input data is written to the
When A8 is high during a WRITE command (WRITEA) , an auto precharge is performed after the last data
The Mode Register can be programmed for burst read and single write. In this mode the write data is only
Command
Command
CLK
A0-7
A8
BA
DQ
CLK
A0-7
A8
BA
DQ
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
ACT
ACT
Xa
Xa
0
Xa
Xa
0
WRITE with Auto-Precharge (BL=4)
Dual Bank Interleaving WRITE (BL=4)
tRCD
tRCD
MITSUBISHI ELECTRIC
Write
Write
Da0
Da0
Y
1
0
Y
0
0
M5M4V4S40CTP-12, -15
Burst Length
Da1
ACT
Da1
Xb
Xb
1
Da2
Da2
tRCD
Da3
Da3
Internal precharge begins
Write
tWR
tWR
Db0
Y
0
1
PRE
Db1
0
0
Db2
tRP
Db3
MITSUBISHI LSIs
ACT
Xa
Xa
0
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