hy5du281622ftp Hynix Semiconductor, hy5du281622ftp Datasheet - Page 17

• Manufacturer Part Number: hy5du281622ftp
• Description: 128mb Ddr Sdram
• Manufacturer: Hynix Semiconductor

Rev. 1.0 /June 2008
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temper-
6. VIN=0 to VDD, All other pins are not tested under VIN =0V.
7. DQs are disabled, VOUT=0 to VDDQ
IDD SPECIFICATION AND CONDITIONS
Test Conditions
Operating Current:
One bank; Active - Precharge; t
per clock cycle; address and control inputs changing once per clock cycle
Operating Current:
One bank; Active - Read - Precharge;
Burst Length=2; t
cycle
Precharge Power Down Standby Current:
All banks idle; Power down mode; CKE=Low, t
Idle Standby Current:
/CS=High, All banks idle; t
CKE=High; address and control inputs changing once per clock cycle.
V
Idle Quiet Standby Current:
/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref
for DQ, DQS and DM
Active Power Down Standby Current:
One bank active; Power down mode; CKE=Low, t
Active Standby Current:
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge; t
DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
Operating Current:
Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per
clock cycle; t
Operating Current:
Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per
clock cycle; t
Auto Refresh Current:
t
refresh
t
Self Refresh Current:
CKE =< 0.2V; External clock on; t
Operating Current - Four Bank Operation:
Four bank interleaving with BL=4, Refer to the following page for detailed test condition
RC
RC
IN
ature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum dif-
ference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum
pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
=t
=t
=V
RFC
RFC
REF
(min) - 8*t
(min) - 14*t
for DQ, DQS and DM
CK
CK
=t
=t
CK
CK
RC
CK
(min); I
(min); DQ, DM and DQS inputs changing twice per clock cycle
=t
CK
RC
for DDR200 at 100Mhz, 10*t
for DDR400 at 200Mhz
(min); t
CK
OUT
=t
CK
RC
=0mA
CK
(min);
CK
=t
=t
=t
RC
CK
CK
(min); t
(min); address and control inputs changing once per clock
(min)
Test Condition
CK
CK
=t
=t
CK
CK
CK
CK
=t
(min)
(min); DQ,DM and DQS inputs changing twice
for DDR266A & DDR266B at 133Mhz; distributed
CK
RC
(min)
=t
RAS
(TA=0 to 70
(max); t
CK
o
C, Voltage referenced to V
=t
HY5DU281622FT(P) Series
CK
(min);
SS
= 0V)
Symbol
I
I
I
I
I
I
I
DD4W
I
I
I
I
I
DD2Q
DD3N
DD2P
DD2F
DD3P
DD4R
DD0
DD1
DD5
DD6
DD7
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