lxt351 Intel Corporation, lxt351 Datasheet - Page 24

• Manufacturer Part Number: lxt351
• Description: T1/e1 Short Haul Transceiver With Crystal-less Jitter Attenuation
• Manufacturer: Intel Corporation

LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
3.0
24
Interrupt Clear
1. In writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in
2. Write a 1 to this bit for normal operation.
Performance
Control #1
Control #2
Control #3
Control #4
Transition
read only registers.
Table 5.
Table 6.
Status
Status
Name
Register
Register Definitions
The LXT351 contains five read/write and two read-only registers that are accessible via the parallel
port.
valid (the address decoder ignores bits A7 and A0) while A0 functions as the read/write (R/W) bit.
the bits in each register.
Note that upon power-up or reset, all registers are cleared to 0.
Register Addresses
Register and Bit Summary
PSR
CR1
CR2
CR3
TSR
CR4
Table 6
ICR
1. x = don’t care
2. Address A0 is the read/write (R/W) bit.
Table 5
Performance Status
Type
R/W
R/W
R/W
R/W
R/W
Transition Status
R
R
identifies the name of each register bit.
Interrupt Clear
Control #1
Control #2
Control #3
Control #4
Name
lists the LXT351 register addresses. Only bits A6 through A1 of the address byte are
reserved
reserved
JASEL1
ESUNF
RESET
JA6HZ
CESU
Register
7
1
1
reserved
reserved
JASEL0
ESOVR
EPAT1
CESO
BIST
6
1
1
Abbr
CR1
CR2
CR3
TSR
PSR
CR4
ICR
reserved
ENCENB
CDFMO
TDFMO
EPAT0
DFMO
SBIST
5
1
Address
EQZMON
reserved
reserved
reserved
reserved
UNIENB
x010000
x010001
x010010
x010011
x010100
x010101
ETAOS
x010111
A7 - A1
Table 7
4
1, 2
2
1
1
1
Bit
through
COL32CM LOS2048
reserved
reserved
reserved
CQRSS
TQRSS
QRSS
3
Table 14
1
1
1
EALOOP
ES64
CAIS
TAIS
EC3
AIS
2
describe the function of
reserved
reserved
reserved
ELLOOP
ESCEN
ZEROV
EC2
1
2
1
1
Datasheet
ERLOOP
CODEV
ESJAM
CLOS
TLOS
EC1
LOS
0