vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 101

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

VSC055-01
Data Sheet
3.2.89 E8h: Master Interface Clock Divider (MICD)
Table 8. Master Interface Clock Divider
The following seven registers comprise the Master Interface function. This function provides the ability to
re-configure 32 of the I/O pins on a pair-by-pair basis as a Master mode two-wire serial interface. Ports 4,
5, 6, and 7 can be re-configured with four interface pairs per port. Each even-numbered port pin can be
configured as an SDA function, with the corresponding odd-numbered port pins configured as an SCL
function.
The following table shows the bit assignments for the Master Interface Clock Divider register.
The following table lists the various divider values that result in common frequencies of operation.
Register Name:
Address:
Reset Value:
Bit
7
6
5:0
Core Clock
10.0 MHz
12.5 MHz
10.0 MHz
12.5 MHz
10.0 MHz
12.5 MHz
8.0 MHz
8.0 MHz
8.0 MHz
Bit Label
MSCE
RES
DIV5-0
DIV5-0
MICD
E8h
0X00_0000b
3Eh
1Fh
27h
31h
13h
18h
04h
06h
07h
Access
R/W
R
R/W
Divider
40
50
63
20
25
32
4
7
8
Description
Master Interface SCL Clock Low Extend
Setting this bit changes the duty cycle of the Master Interface SCL clock output
from a 50% low-50% high duty cycle to a 75% low-25% high duty cycle. This
allows for better matching of fast mode (400 kHz) interface timings.
After a reset or power on, this bit is cleared, enabling the default duty cycle.
Reserved.
Master Interface Clock Divider
These six bits determine the SCL clock frequency of the Master Interface. The
Master Interface uses a four-cycle state machine to drive the SCL output. All
timings for the Master Interface are based on this four-cycle state machine. The
frequency of operation desired is based on the divider value along with the core
clock frequency of the VSC055-01. For the various divider values that result in
common frequencies of operation, see
101 of 133
SM
4
4
4
4
4
4
4
4
4
Master Interface SCL Clock Frequency
50.0 kHz
50.0 kHz
49.6 kHz
100.0 kHz
100.0 kHz
97.6 kHz
400.0 kHz
357.1 kHz
390.6 kHz
Table 8,
page 101.
January 2008
Revision 4.1