vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 35

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

VSC055-01
Data Sheet
3.2.22 25h: Port Bypass Control 5 (PBC5)
The following table shows the bit assignments for the Port Bypass Control 5 register. This register
functions the same as the Port Bypass Control 0 register except it affects the P4.3 and P4.2 pins.
Register Name:
Address:
Reset Value:
Bit
7
6
5:2
1
0
Bit Label
PBCEN
SDIEN
RES
FB
SD
PBC5
25h
00XX_XX1Xb
Access
R/W
R/W
R
R/W
R/W
Description
Port Bypass Control Enable
When this bit is set, P4.3 and P4.2 are automatically configured as an FB
output pin and an SD input pin. Configurations for these I/O pins that may have
been previously enabled through other control registers are overridden, except
for the bypass select function (bits 6 and 5 of the appropriate bit control
registers).
When this bit is reset, the remaining bits in this register have no effect on the
operation of P4.3 and P4.2.
Signal Detected Interrupt Enable
When this bit is set, the SD input generates an interrupt if a transition occurs on
the pin. If a transition occurs, the INT# pin asserts and a binary value equal to
the address of this register appears in the BCIS register.
When this bit is reset, transitions on the signal detected input do not generate
an interrupt condition.
Reserved.
Force Bypass
This bit controls the P4.3 I/O pin, which is configured as a totem pole output by
setting the PBCEN bit.
When this bit is set, the force bypass input of a PBC/CRU/SDU function is not
enabled and the port bypass circuit is in Normal mode.
When this bit is reset, the force bypass function of a PBC/CRU/SDU function is
enabled and the port bypass circuit is in Bypass mode.
This register bit is automatically cleared when the synchronized and filtered
P4.2 input is LOW, resulting in a maximum latency of 400 ns from detection of
the loss of a high-speed signal to the de-assertion of the P4.3 output.
Note: Because all I/O pins on the device power up as inputs with weak internal
pull-up resistors, it is possible to define the default state of the force bypass
function by using an external pull-down resistor. The default state of the I/O can
be determined by reading this register, because the read value of the register
bits is always available through an input synchronizer and filter. After the
default state is determined, write the default value to the FB bit of this register
and set the PBCEN bit to ensure that the port bypass control functions are
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains HIGH.
Signal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P4.2
I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU
function.
If this bit is set, the signal detect unit detects a high-speed signal.
If this bit is reset, the signal detect unit does not detect a high-speed signal.
35 of 133
January 2008
Revision 4.1