vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 105
vsc055xkm-01
Manufacturer Part Number
vsc055xkm-01
Description
Enhanced I?c Backplane Controller
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.VSC055XKM-01.pdf
(133 pages)
- Current page: 105 of 133
- Download datasheet (2Mb)
VSC055-01
Data Sheet
(repeat steps 5-8 if there are multiple register address bytes or
data bytes)
Send data written to slave device register with a stop:
9)
10) Write 5Ah to the MIC register (command)
11) Poll the MIS register until bit 0 = 1
12) Test bit 1, if set continue, if clear then the slave device
did not acknowledge
The sequence for normal two-wire serial protocol compliant read
operations is:
1) Issue start bit, send the slave device address and write bit
(0) in LSB
2) Send the slave device's register address, this can zero bytes
or in some slave devices this may be multiple bytes.
3) Issue another start bit (re-start condition), send the slave
device address and read bit (1) in the LSB.
4) Read a byte from the slave device, or multiple bytes if the
slave device supports sequential reads.
4a) For sequential reads, issue the Read Byte with ACK command
(54h) for all but the last byte.
4b) Issue the Read Byte with stop, no ACK command (52h) for the
last byte.
Pseudo-code to perform two-wire serial protocol compliant reads
using this core:
Send slave device address:
1)
2)
3)
4)
did not respond
Send register address:
5)
6)
7)
8)
did not acknowledge
(repeat steps 5-8 if there are multiple register address bytes)
Issue re-start with slave device address and read bit:
9)
10) Write 59h to the MIC register (command)
11) Poll the MIS register (status) until bit 0 = 1
12) Test bit 1, if set continue, if clear then the slave device
did not acknowledge
<data byte>
<{slave_address[6:0],1'b0}>
Write 59h to the MIC register (command)
Poll the MIS register (status) until bit 0 = 1
Test bit 1, if set continue, if clear then the slave device
<slave's register address>
Write 58h to MIC register (command)
Poll the MIS register (status) until bit 0 = 1
Test bit 1, if set continue, if clear then the slave device
<{slave_address[6:0],1'b1}>
-->
MID register (data)
105 of 133
-->
-->
-->
MID register (data)
MID register (data)
MID register (data)
January 2008
Revision 4.1
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