MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 35

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

4.2.5a Transmit and Receive Interrupt Descriptor Rings
The MK50H28 has two descriptor ring structures for the purpose of queuing Transmit and Receive inter-
rupts. The pointers to these two descriptor rings are located at IADR+24 through IADR+30. These de-
scriptor rings consist of 128 entries. Each entry consists of two 16-bit words containing the 24-bit ad-
dress of the Contest Table entry (XCTADR, RCTADR)corresponding to the interrupt, a 7-bit field for the
descriptor index (CURXD, CURRD) into the associated descriptor ring, and a SRVC bit to indicate
whether the interrupt has been serviced. No entry will be made in the Receive Interrupt Descriptor Ring
(nor will interrupt be generated) if bit RINTD (CTADR+12 <10>) is set; likewise for TINTD (TMD0<08>).
4.2.5a.1 Transmit Interrupt Descriptor Ring Entry
4.2.5a.2 Receive Interrupt Descriptor Ring Entry
07:00/15:00
07:00/15:00
14:08
14:08
BIT
BIT
15
15
XCTADR
RCTADR
CURRD
CURXD
NAME
NAME
SRVC
SRVC
TINTMD0
TINTMD1
RINTMD0
RINTMD1
This bit is set by the MK50H28 when it writes an interrupt to the Interrupt Descriptor Ring
and should be cleared by the host when it Services the interrupt. If it attempts to write TX
interrupt information to a Transmit Interrupt Ring entry for which SRVC is not clear , the
MK50H28 will issue PPRIM 7 with PPARM=0 (Tx Int MISS) in addition to giving TINT.
Specifies the current transmit descriptor (0-127) at the time the interrupt ocurred.
Transmit Context Table Address. Indicates address of the CT entry at the time the
interrupt ocurred. NOTE: XCTADR specifies which CT entry, and CURXD specifies the
descriptor within the Tx Ring associated with the CT entry for which the interrupt ocurred.
This bit is set by the MK50H28 when it writes an interrupt to the Interrupt Descriptor Ring
and should be cleared by the host when it Services the interrupt. The MK50H28 will issue
PPRIM 7 with PPARM=1(Rx Int MISS) in addition to RINT, and it will discard the received
frame if it is unable to write to the Rececive Interrupt ring due to SRVC not being clear.
Specifies the current receive descriptor (0-127) at the time the interrupt ocurred.
Receive Context Table Address. Indicates address of the CT entry at the time the
interrupt ocurred. NOTE: RCTADR specifies the CT entry, and CURRD specifies the
descriptor within the Rx Ring associated with the CT entry for which the interrupt ocurred.
1
5
S
R
V
C
1
5
S
R
V
C
1
4
1
4
1
3
1
3
CURXD (0-127)
CURRD (0-127)
1
2
1
2
1
1
1
1
0
0
0
0
XCTADR<15:00>
RCTADR<15:00>
0
9
0
9
0
8
0
8
DESCRIPTION
DESCRIPTION
0
7
0
7
0
6
0
6
XCTADR<23:16>
RCTADR<23:16>
0
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
0
MK50H28
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