MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 5

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

Table 1: PIN DESCRIPTION (continued)
SIGNAL NAME
BUSRQ
READY
HOLD
HLDA
ADR
ALE
AS
CS
PIN(S)
[19]
[20]
[21]
[22]
[23]
[24]
17
18
19
20
21
22
IO/OD
IO/OD
TYPE
O/3S
I
I
I
If CSR4<00> BCON = 1,
Byte selection is done using the BYTE line and DAL<00> latched during the
address portion of the bus transaction. MK50H28 drives BYTE only as a Bus
Master and ignores it when a Bus Slave. Byte selection is done as outlined
in the following table.
BYTE
LOW
LOW
HIGH
HIGH
BUSAKO is a bus request daisy chain output. If MK50H28 is not requesting
the bus and it receives HLDA, BUSAKO will be driven low. If MK50H28 is
requesting the bus when it receives HLDA, BUSAKO will remain high
Note: All transfers are entire word unless the MK50H28 is configured for 8 bit
operation.
Pin 17 is configured through bit 0 of CSR4.
If CSR4<00> BCON = 0,
HOLD request is asserted by MK50H28 when it requires a DMA cycle, if
HLDA is inactive, regardless of the previous state of the HOLD pin. HOLD is
held low for the entire ensuing bus transaction.
If CSR4<00> BCON = 1,
BUSRQ is asserted by MK50H28 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held low
for the entire ensuing bus transaction.
The active level of ADDRESS STROBE is programmable through CSR4.
The address portion of a bus transfer occurs while this signal is at its
asserted level. This signal is driven by MK50H28 while it is the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01> ACON = 0,
ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define
the address portion of the transfer. As ALE, the signal transitions from high
to low during the address portion of the transfer and remains low during the
data portion.
If CSR4<01> ACON = 1,
As AS, the signal pulses low during the address portion of the bus transfer.
The low to high transition of AS can be used by a slave device to strobe the
address into a register.
AS is effectively the inversion of ALE.
HOLD ACKNOWLEDGE is the response to HOLD. When HLDA is low in
response to MK50H28’s assertion of HOLD, the MK50H28 is the Bus
Master. HLDA should be deasserted ONLY after HOLD has been released
by the MK50H28.
CHIP SELECT indicates, when low, that the MK50H28 is the slave device
for the data transfer. CS must be valid throughout the entire transaction.
ADDRESS selects the Register Address Port or the Register Data Port. It
must be valid throughout the data portion of the transfer and is only used by
the chip when CS is low.
ADR
LOW
HIGH
When the MK50H28 is a Bus Master, READY is an asynchronous
acknowledgement from the bus memory that memory will accept data in a
WRITE cycle or that memory has put data on the DAL lines in a READ cycle.
I/O PIN 15 = BYTE (O/3S)
I/O PIN 16 = BUSAKO (O)
LOW
HIGH
REGISTER ADDRESS PORT
DAL<00>
LOW
HIGH
REGISTER DATA PORT
I/O PIN 17 = HOLD
I/O PIN 17 = BUSRQ
I/O PIN 18 = ALE
I/O PIN 18 = AS
PORT
TYPE OF TRANSFER
UPPER BYTE
ENTIRE WORD
ILLEGAL CONDITION
LOWER BYTE
DESCRIPTION
MK50H28
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