alc885-gr Realtek Semiconductor Corporation, alc885-gr Datasheet - Page 89
alc885-gr
Manufacturer Part Number
alc885-gr
Description
7.1+2 Channel High-performance Hda Codec With Content Protection
Manufacturer
Realtek Semiconductor Corporation
Datasheet
1.ALC885-GR.pdf
(98 pages)
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9.2.3.
9.2.4.
The ALC885 does not support codec test mode or Automatic Test Equipment (ATE) mode.
7.1+2 Channel High-Performance HDA Codec
With Content Protection
Parameter
S/PDIF-OUT Frequency
S/PDIF-OUT Period
S/PDIF-OUT Jitter
S/PDIF-OUT High Level Width
S/PDIF-OUT Low Level Width
S/PDIF-OUT Rising Time
S/PDIF-OUT Falling Time
S/PDIF-IN Period
S/PDIF-IN Jitter
S/PDIF-IN High Level Width
S/PDIF-IN Low Level Width
*1: Bit parameters for 48kHz sample rate of S/PDIF-OUT
*2: Bit parameters for 48kHz sample rate of S/PDIF-IN
S/PDIF Output and Input Timing
Test Mode
*2
*1
V
V
IH
IL
Table 92. S/PDIF Output and Input Timing
T
Symbol
Figure 17. Output and Input Timing
rise
T
T
T
T
T
T
T
T
T
T
cycle
cycle
jitter
High
jitter
High
Low
Low
-
rise
fall
T
high
156.2 (48%)
156.2 (48%)
146.4 (45%)
146.4 (45%)
Minimum
T
T
cycle
fall
-
-
-
-
-
-
-
81
T
low
162.8 (50%)
162.8 (50%)
162.8 (50%)
162.8 (50%)
Typical
3.072
325.6
325.6
2.0
2.0
-
-
V
OL
V
OH
169.2 (52%)
169.2 (52%)
Maximum
179 (55%)
179 (55%)
V
10
t
4
-
-
-
-
-
ALC885 Series
Datasheet
ns (%)
ns (%)
ns (%)
ns (%)
Units
MHz
ns
ns
ns
ns
ns
ns
Rev. 1.1
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