rf2059sr RF Micro Devices, rf2059sr Datasheet - Page 12

• Manufacturer Part Number: rf2059sr
• Description: High Performance Rf Pll/vco With Rf Mixers For Wlan Band Shifters
• Manufacturer: RF Micro Devices

RF2059
If automatic loop bandwidth correction is enabled the charge pump current is set by the calibration algorithm based upon the
VCO gain. For more information on the VCO gain calibration, which is disabled by default, please refer to the RF205x Calibra-
tion User Guide.
The phase detector will operate with a maximum input frequency of 52MHz.
Note that for high phase detector frequencies, the divider ratio decreases. For N<28 the FLL_FACT register needs to be
changed to 00 from the default value of 01. This is to ensure correct VCO band selection.
Loop Filter
The PLL may be designed to use an active or a passive loop filter as required. The internal configuration of the chip is shown
below. If the CFG1:LF_ACT bit is asserted high, the op-amp will be enabled. If the CFG1:LF_ACT bit is asserted low, the internal
op-amp is disabled and a high impedance is presented to the LFILT1 pin. The RF205x Programming Tool software can assist
with loop filter designs. Because the op-amp is used in an inverting configuration in active mode, when the passive loop filter
mode is selected the phase-detector polarity should be inverted. For active mode, CFG1:PDP=1, for passive mode,
CFG1:PDP=0.
The charge pump output voltage compliance range is typically +0.7V to +1.5V. For applications using a passive loop filter VCO
coarse tuning must be performed regularly enough to ensure that the VCO tuning voltage falls within this compliance range at
all temperatures. The active loop filter maintains the charge pump output voltage in the center of the compliance range, and
the op-amp provides a wider VCO tuning voltage range, typical 0V to +2.4V.
Crystal Oscillator
The PLL may be used with an external reference source, or its own crystal oscillator. If an external source (such as a TCXO) is
being used it should be AC-coupled into one of the XO inputs, and the other input should be AC-coupled to ground.
A crystal oscillator typically takes many milliseconds to settle, and so for applications requiring rapid pulsed operation of the
PLL (such as a TDMA system, or Rx/Tx half-duplex system) it is necessary to keep the XO running between bursts. However,
when the PLL is used less frequently, it is desirable to turn off the XO to minimize current draw. The REFSTBY register is pro-
vided to allow for either mode of operation. If REFSTBY is programmed high, the XO will continue to run even when ENBL is
asserted low. Thus the XO will be stable and a clock is immediately available when ENBL is asserted high, allowing the chip to
assume normal operation. On cold start, or if REFSTBY is programmed low, the XO will need a warm-up period before it can pro-
vide a stable clock. The length of this warm-up period will be dependant on the crystal characteristics.
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LFILT1
+1.1V
+
LF_ACT=TRUE
-
LFILT2
To VCO Tuning
LFILT3
DS100630