k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 11

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
CAS LATENCY (READ LATENCY)
data. The latency can be set to 7~12 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will
be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency set-
ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
RDQS
RDQS
/CK
CK
/CK
CK
DQ
DQ
SPEED
-BC12
-BC14
-BJ1A
-BJ11
Burst Length = 4 in the cases shown
Shown with nominal t
READ
CL=12
READ
≤ 1000
T0
T0
AC
and nominal t
CL=11
≤ 900
≤ 800
DON’T CARE
NOP
NOP
T6
T5
Allowable operating frequency (MHz )
DSDQ
CAS Latency
CL=10
≤ 700
11 / 54
-
CL = 8
CL = 7
TRANSITIONING DATA
NOP
NOP
T7
T6
CL=9
-
-
256M GDDR3 SDRAM
CL=8
NOP
NOP
T8
T7
-
-
Rev. 1.3 May 2007
T8n
T7n
CL=7
-
-