k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 25

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
All DQs and RDQS, collectively
All DQs and RDQS, collectively
Data Output Timing (1) - t
All DQs and RDQS, collectively
Data Output Timing (2) - t
DQ(First data no longer valid)
Note : 1. t
2. t
3. t
4. t
5. The data valid window is derived for each RDQS transitions and is defined by t
6. There are 4 RDQS pins for this device with RDQS0 in relation to DQ0-DQ7, RDQS1 in relation DQ8-DQ15, RDQS2 in
7. This diagram only represents one of the four byte lanes.
8. t
DQ(Last data valid)
with the last valid transition of DQs.
relation to DQ16-24 and RDQS3 in relation to DQ25-DQ31.
DQSQ
AC
DQHP
AC
DQSQ
is show in the nominal case
represents the relationship between DQ, RDQS to the crossing of CK and /CK.
is derived at each RDQS clock edge and is not cumulative over time and begins with first DQ transition and ends
is the lesser of tDQSL or tDQSH strobe transition collectively when a bank is active.
represents the skew between the 8 DQ lines and the respective RDQS pin.
RDQS
RDQS
RDQS
CK#
CK
CK#
CK
1.6
1.6
1.6
5
5
5
DQSQ
DQSQ
, t
, t
QH
QH
T0
T0
and Data Valid Window
and Data Valid Window
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T1
T1
t
DQSQ
t
DQSQ
t
AC
t
CH
2
t
AC
(MIN)
(MIN)
2
(MAX)
(MAX)
t
CL
T2
T2
T2
t
T2
t
DQSH
CH
t
DV
T2
T2
4
T2
T2n
DV
t
256M GDDR3 SDRAM
4
DQSH
T2n
.
T2n
T2n
t
t
DQSL
CL
4
t
t
T2n
DV
DQSH
T2n
T2n
4
T3
t
4
DQSL
Rev. 1.3 May 2007
T3
t
4
DQSQ
t
T3
DQSQ
T3
4
t
t
DQSL
DV
T3
2
2
T3
T3
T3n
(MAX)
4
(MIN)
T3n
4
T3n
T3n
T3n
t
DV
T3n
T3n
T4
4
T4