gm76c256c Hynix Semiconductor, gm76c256c Datasheet - Page 6
gm76c256c
Manufacturer Part Number
gm76c256c
Description
32k X8 Bit 5.0v Low Power Cmos Slow Sram
Manufacturer
Hynix Semiconductor
Datasheet
1.GM76C256C.pdf
(11 pages)
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TIMING DIAGRAM
READ CYCLE 1
OE
CS
Data
Out
Note(READ CYCLE):
1. t
2. At any given temperature and voltage condition, t
3. /WE is high for the read cycle.
READ CYCLE 2
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS= V
3. /OE =V
Rev 03 / Apr. 2000
ADDR
ADDR
Data
Out
referenced to output voltage levels.
and from device to device.
CHZ
and t
IL
.
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and arenot
High-Z
Previous Data
tOH
tCLZ
tAA
tAA
tACS
tOLZ
IL.
tOE
tRC
tRC
CHZ
max. is less than t
Data Valid
Data Valid
tOHZ
CLZ
tCHZ
tOH
tOH
min. both for a given device
GM76C256C Series
5