gm76c256c Hynix Semiconductor, gm76c256c Datasheet - Page 8

• Manufacturer Part Number: gm76c256c
• Description: 32k X8 Bit 5.0v Low Power Cmos Slow Sram
• Manufacturer: Hynix Semiconductor

Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
2. t
3. t
4. t
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,
6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high
7. D
8. D
DATA RETENTION CHARACTERISTIC
T
Symbol
V
I
tCDR
tR
Notes
1. Typical values are under the condition of T
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
Rev 03 / Apr. 2000
CCDR
A
DR
or /WE going high.
among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high
and /WE going high. t
CW
AS
WR
input of opposite phase of the output must not be applied because bus contention can occur.
impedance state.
= 0 C to 70 C (Normal) / -25 C to 85 C (Extended) unless otherwise specified.
OUT
OUT
is measured from the address valid to the beginning of write.
is measured from the later of /CS going low to the end of write .
is measured from the end of write to the address change. t
is the same phase of the latest written data in this write cycle.
is the read data of the new address.
2.2V
VCC
4.5V
VDR
CS
VSS
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operating Recovery Time
Parameter
tCDR
WP
is measured from the beginning of write to the end of write.
DATA RETENTION MODE
CS>VCC-0.2V
CS>Vcc-0.2V,
V
Vcc=3.0V,
/CS>Vcc - 0.2V,
V
V
See Data Retention
Timing Diagram
IN
IN
IN
< Vss + 0.2V
> Vcc - 0.2V or V
> Vcc - 0.2V or
A
= 25 C.
Test Condition
tR
IN
< Vss + 0.2V
WR is
applied in case a write ends as /CS,
L
LL
LE
LLE
tRC
GM76C256C Series
Min
2.0
0
-
-
-
-
(2)
Typ
0.5
0.5
1
1
-
-
-
Max
15
20
10
7
-
-
-
7
Unit
uA
uA
uA
uA
ns
ns
V