gl846 Genesys Logic, gl846 Datasheet - Page 33

• Manufacturer Part Number: gl846
• Description: High Speed Usb 2.0 2-in-1 Scanner Controller With Fast Adf
• Manufacturer: Genesys Logic

0 Enable CCD CP & RS signals under CCD TG position as illustrated.
©2000-2007 Genesys Logic Inc. - All rights reserved.
Offset 17h ……………………………………………..…………..……….……. Default value = 8’h14
Offset 18h ……………………………………………..…………..……..………. Default value = 8’h00
7-6 TGMODE [1:0] To set CCD TG mode.
5-0 TGW [5:0]
6-5 DCKSEL1 [1:0] 00 Speed 1: one CCD clock per system pixel time in shifting dummy lines.
1-0 CKSEL [1:0]
3-2 CKDELAY [1:0] 00 No delay
TGMODE1 TGMODE0
0 CTRLDIS
Note: It cannot be programmed to logic zero.
7 CNSET
4 CKTOGGLE
CNSET
R/W
R/W
GL846 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF
DCKSEL1 DCKSEL0
R/W
R/W
1 Disable CCD CP & RS signals under CCD TG position as illustrated.
00 normal CCD TG type.
01 CCD TG control with dummy line.
10 CCD TG control with dummy lines for transparency scanning type.
11 reserved for ASIC simulation.
To set CCD TG plus width (in pixel time).
0 Select TG and clock to be non-Canon CIS style.
1 Select TG and clock to be Canon CIS style.
01 Speed 2: two CCD clock per system pixel time in shifting dummy lines.
10 Speed 3: three CCD clock per system pixel time in shifting dummy lines.
11 Speed 4: four CCD clock per system pixel time in shifting dummy lines.
0 One cycle per pixel.
1 Half cycle per pixel for CCD clock 1 & 2.
01 Delay one system clock for CCD Clock 1/2.
10 Delay two systems clock for CCD Clock 1/2.
11 Delay three systems clock for CCD Clock 1/2.
00 Speed 1: one CCD clock per system pixel time in capturing image.
01 Speed 2: two CCD clock per system pixel time in capturing image.
TGW5
R/W
R/W
CKTOGGLE
TGW4
R/W
R/W
CKDELAY1 CKDELAY0
TGW3
R/W
R/W
TGW2
R/W
R/W
CKSEL1
TGW1
R/W
R/W
CKSEL0
TGW0
Page 33
R/W
R/W