gl846 Genesys Logic, gl846 Datasheet - Page 67

• Manufacturer Part Number: gl846
• Description: High Speed Usb 2.0 2-in-1 Scanner Controller With Fast Adf
• Manufacturer: Genesys Logic

©2000-2007 Genesys Logic Inc. - All rights reserved.
3
2
1
0
Offset B9h ……..……..………………....………..…………..….………..…..…. Default value = 8’h00
7
6
5
4
Offset BAh ……..……..………………....………..…………..….………..…..…. Default value = 8’h00
7
6
3
2-0 TSHMSKB [2:0]
CCD_OUT
TCK_EN
R/W
R/W
SW2_EN
SW2_SEL
SW4_EN
SW4EXCHG
TCK_EN
TCK_SEL
TCK4_DIS
TCK3_DIS
TCK1_DIS
CCD_OUT
AV_EN
GL846 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF
TCK_SEL TCK4_DIS TCK3_DIS TCK1_DIS
AV_EN
R/W
R/W
Enable special CCD timing of CCD SW2 for Toshiba’s application
0 CCD SW2 and CCD SW5 timing control is based on internal CCD_CNX
1 CCD SW2 and CCD SW5 timing control is based on internal SH_CNT
Enable special CCD timing of CCD SW4 for Toshiba’s application
Control CCD SW4 shutter for Multi-SH apllication
0 Select traditional CCD PHI clocks timing
1 Select special CCD PHI clocks timing such as NEC 8884 or Toshiba CCD
0 CCD PHI clocks timing is based on internal CCD_CNX counter of ASIC
1 CCD PHI clocks timing is based on internal SH_CNT counter of ASIC
0 Enable CCD PHI4 clock output when ASIC works on special CCD timing
1 Disable CCD PHI4 clock output when ASIC works on special CCD timing
0 Enable CCD PHI3 clock output when ASIC works on special CCD timing
1 Disable CCD PHI3 clock output when ASIC works on special CCD timing
0 Enable CCD PHI1 & 2 clocks output when ASIC works on special CCD
1 Disable CCD PHI1 & 2 clocks output when ASIC works on special CCD
different exposure time and TSH_EN is set to “1” at the same time
Select SH3 operation behavior for special CCD application when CCD works on
Enable internal CCD signal outputs including sh_enb, sh_enbx and ccd_cnt[2:0]
for external CPLD implementation to meet special CCD timing
Enable switch control for special CCD or CIS
counter of ASIC
counter of ASIC
operation
operation
operation
operation
timing operation
timing operation
TSHMSKG2 TSHMSKG1 TSHMSKG0 TSHMSKR2 TSHMSKR1 TSHMSKR0
R/W
R/W
R/W
R/W
R/W
R/W
TSHMSKB2 TSHMSKB1 TSHMSKB0
R/W
R/W
R/W
R/W
Page 67
R/W
R/W