UPD705100GJ-100-8 NEC [NEC], UPD705100GJ-100-8 Datasheet - Page 38

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UPD705100GJ-100-8

Manufacturer Part Number
UPD705100GJ-100-8
Description
V830TM 32-BIT MICROCONTROLLER
Manufacturer
NEC [NEC]
Datasheet

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38
Instruction
SAR
SATADD3
SATSUB3
SETF
SHL
SHLD3
reg1 ,reg2
imm5, reg2
reg1, reg2,
reg3
reg1, reg2,
reg3
imm5, reg2
reg1, reg2
imm5, reg2
reg1, reg2,
reg3
Operand(s)
I
II
VIII
VIII
II
I
II
VIII
Format
CY
-
-
OV
0
0
0
0
-
-
S
-
-
Z
-
-
Arithmetic right shift. reg2 is arithmetically
shifted to the right by the displacement
specified by the low-order five bits of reg1
(MSB value is copied to the MSB in sequence).
The result is written into reg2.
Arithmetic right shift. reg2 is arithmetically
shifted to the right by the displacement specified
by imm5, zero-extended to a word. The result is
written into reg2.
Saturatable addition. reg1 and reg2 are added
together as signed integers.
[If no overflow has occurred:]
[If an overflow has occurred:]
Saturatable subtraction. reg1 is subtracted from
reg2 as signed integers.
[If no overflow has occurred:]
[If an overflow has occurred:]
Set flag condition. reg2 is set to 1 if the
condition specified by the low-order four bits of
imm5 matches the condition flag; otherwise it is
set to 0.
Logical left shift. reg2 is logically shifted to the
left (0 is put on the LSB) by the displacement
specified by the low-order five bits of reg1. The
result is written into reg2.
Logical left shift. reg2 is logically shifted to the
left by the displacement specified by imm5,
zero-extended to a word. The result is written
into reg2.
Left shift of concatenation. The 64 bits
consisting of reg3 (high order) and reg2
(low order) are logically shifted to the left by the
displacement specified by the low-order five bits
of reg1. The high-order 32 bits of the result are
written into reg3.
The result is written into reg3.
The SAT bit is set. If the result is positive,
the positive maximum is written into reg3; if
the result is negative, the negative maximum
is written into reg3.
The result is written into reg3.
The SAT bit is set. If the result is positive,
the positive maximum is written into reg3; if
the result is negative, the negative maximum
is written into reg3.
Function
PD705100

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