UPD705100GJ-100-8 NEC [NEC], UPD705100GJ-100-8 Datasheet - Page 41

• Manufacturer Part Number: UPD705100GJ-100-8
• Description: V830TM 32-BIT MICROCONTROLLER
• Manufacturer: NEC [NEC]

12. INTERRUPTS AND EXCEPTIONS
nonmaskable interrupts. In contrast, exceptions are events which are directly related to program execution. Interrupts
and exceptions do not differ greatly in their control flow, but interrupts are assigned higher handling priorities than
exceptions. Fatal exceptions, however, are assigned higher priorities than interrupts.
interrupt, or nonmaskable interrupt occurs, control is passed to a handler at an address which is predetermined a given
cause. The cause of an exception can be identified by means of the exception code stored in the ECR (Exception
Cause Register). The pertinent handler analyzes the contents of the ECR so that it can handle the exception or interrupt
appropriately.
Reset
Fatal exception
NMI
Double exception
TRAP instruction (parameter 0 1n)
TRAP instruction (parameter 0 0n)
Invalid operation code
Division by zero
Interrupt level n (n = 0-15)
Interrupts are events which occur independently of program execution. They are classified into maskable and
Under the V830 architecture, the following interrupts and exceptions may occur. When an exception, maskable
Notes 1. Level n is represented by a hexadecimal number (n = 0-F).
2. Exception code of the exception which caused the double exception
Exception/interrupt
HWCC.IHA = 0
HWCC.IHA = 1
Table 12-1. Exception/Interrupt Source Codes
Interrupt
Exception
Interrupt
Exception
Exception
Exception
Exception
Exception
Interrupt
Category
Exception code
FFF0H
FFD0H
Note 2
FFBnH
FFAnH
FF90H
FF80H
FEn0H
ECR
-
Note 1
FFFFFFF0H
FFFFFFE0H
FFFFFFD0H
FFFFFFD0H
FFFFFFB0H
FFFFFFA0H
FFFFFF90H
FFFFFF80H
FFFFFEn0H
FE0000n0H
address
Handler
Note1
PD705100
Indefinite
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