74AUP2G132GT,115 NXP Semiconductors, 74AUP2G132GT,115 Datasheet
74AUP2G132GT,115
Specifications of 74AUP2G132GT,115
74AUP2G132GT-G
935280733115
Available stocks
Related parts for 74AUP2G132GT,115
74AUP2G132GT,115 Summary of contents
Page 1
Low-power dual 2-input NAND Schmitt trigger Rev. 4 — 4 November 2010 1. General description The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accept standard input signals. They are capable of transforming slowly changing input signals ...
Page 2
... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74AUP2G132DC −40 °C to +125 °C 74AUP2G132GT −40 °C to +125 °C 74AUP2G132GF −40 °C to +125 °C 74AUP2G132GD −40 °C to +125 °C 74AUP2G132GM −40 °C to +125 °C 74AUP2G132GN − ...
Page 3
... NXP Semiconductors 7. Pinning information 7.1 Pinning 74AUP2G132 GND 4 001aaf164 Fig 4. Pin configuration SOT765-1 74AUP2G132 GND 4 Transparent top view Fig 6. Pin configuration SOT996-2 7.2 Pin description Table 3. Pin description Symbol Pin SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 1A 1B GND 4 1Y 74AUP2G132 ...
Page 4
... NXP Semiconductors 8. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current ...
Page 5
... NXP Semiconductors 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 25 °C T amb V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF ΔI additional power-off OFF leakage current ...
Page 6
... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF ΔI additional power-off OFF leakage current I supply current CC ΔI additional supply current CC = −40 °C to +125 °C ...
Page 7
... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ΔI additional power-off OFF leakage current I supply current CC ΔI additional supply current CC − 0.6 V, other input at V [1] One input 12. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see ...
Page 8
... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions propagation delay nY; see pF and power dissipation MHz capacitance [1] All typical values are measured at nominal V [ the same as t and PLH PHL [ used to determine the dynamic power dissipation (P PD × ...
Page 9
... NXP Semiconductors 13. Waveforms Measurement points are given in Logic levels: V and Fig 8. The data input (nA or nB) to output (nY) propagation delays Table 9. Measurement points Supply voltage Output 0.5 × 3.6 V Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance. ...
Page 10
... NXP Semiconductors 14. Transfer characteristics Table 11. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions V positive-going see T+ threshold voltage Figure negative-going see T− threshold voltage Figure hysteresis voltage ( Figure Figure 15. Waveforms transfer characteristics T− Fig 10. Transfer characteristic ...
Page 11
... NXP Semiconductors Fig 12. Typical transfer characteristics 3 Fig 13. Typical transfer characteristics; V 74AUP2G132 Product data sheet 240 I CC (μA) 160 0.4 0.8 1 1200 I CC (μA) 800 400 0 0 1.0 2 All information provided in this document is subject to legal disclaimers. Rev. 4 — 4 November 2010 ...
Page 12
... NXP Semiconductors 16. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula add P = additional power dissipation (μW); add f = input frequency (MHz input rise time (ns input fall time (ns ΔI CC(AV) Average ΔI (1) Positive-going edge ...
Page 13
... NXP Semiconductors 17. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 14
... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
Page 15
... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
Page 16
... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 18. Package outline SOT996-2 (XSON8U) ...
Page 17
... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...
Page 18
... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
Page 19
... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
Page 20
... NXP Semiconductors 18. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 19. Revision history Table 13. Revision history Document ID Release date 74AUP2G132 v.4 20101104 • Modifications: Added type number 74AUP2G132GF (SOT1089/XSON8 package). ...
Page 21
... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
Page 22
... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 21. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AUP2G132 Product data sheet Low-power dual 2-input NAND Schmitt trigger 20 ...
Page 23
... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Functional description . . . . . . . . . . . . . . . . . . . 4 9 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 13 Waveforms ...