PLL500-20 PhaseLink (PLL), PLL500-20 Datasheet - Page 2
![no-image](/images/no-image-200.jpg)
PLL500-20
Manufacturer Part Number
PLL500-20
Description
, Low Phase Noise Vcxo ( 20MHz to 52MHz )
Manufacturer
PhaseLink (PLL)
Datasheet
1.PLL500-20.pdf
(5 pages)
PAD DESCRIPTION
See also pad coordinates table at the end of this document.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature*
Name
XOUT
GND
VDD
CLK
VIN
XIN
OE
OE
Number
PARAMETERS
1
2
3
4
5
6
7
8
Type
O
P
P
I
I
I
I
I
Crystal output pin.
Output Enable input pin. Tri-states output if low. Enables output if high.
Frequency control voltage input pin.
Ground pin.
Output clock pin.
+3.3V VDD power supply pin.
Output Enable input pin. Tri-states output if low. Enables output if high.
Crystal input pin.
Low Phase Noise VCXO (20MHz to 52MHz)
SYMBOL
V
V
T
V
CC
O
S
I
Description
Preliminary
MIN.
-
-
-
-65
-40
0.5
0.5
0.5
PLL500-20
V
V
MAX.
CC
CC
260
150
85
7
+
+
0.5
0.5
Rev 1/07/03 Page 2
UNITS
V
V
V
C
C
C