PLL502-10 PhaseLink (PLL), PLL502-10 Datasheet

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PLL502-10

Manufacturer Part Number
PLL502-10
Description
, 12-25MHz In, 750kHz-400MHz Out, CMOS, Pecl, LVDS
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTIONS
The PLL502-10 is a monolithic low jitter and low
phase noise (-140dBc/Hz @ 10kHz offset) VCXO IC
Die, with CMOS, LVDS and PECL output, covering
the 750kHz to 400MHz output range. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
The same die can be used as a VCXO with output
frequencies ranging from F
thanks to frequency selector pads. This makes the
PLL502-10 ideal as a universal die for applications
ranging from ADSL to SONET.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
XOUT
SEL
XIN
750kHz to 400MHz output range.
Low phase noise output (@ 10kHz frequency
offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz).
Selectable CMOS, PECL and LVDS output.
12 to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Wide pull range (+/-190 ppm)
3.3V operation.
Available in DIE (65 mil x 62 mil).
750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
VARICAP
Reference
VCON
XTAL
Divider
OSC
Divider
Detector
Phase
VCO
Charge
Pump
Loop
Filter
+
XIN
/ 16 to F
VCO
OE
XIN
x 16
CLKBAR
CLK
DIE CONFIGURATION
DIE SPECIFICATIONS
OUTPUT SELECTION AND ENABLE
Pad #9:
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “0”
Y
OE_SELECT
X
1 (Default)
OUTSEL1
(Pad #9)
Pad #18
Pad dimensions
(0,0)
Reverse side
Bond to GND to set to “0”, bond to VDD to set to “1”
Logical states defined by CMOS levels if OE_SELECT is “1”
Thickness
0
0
1
1
0
Name
26
27
28
29
30
31
Size
25
1
24
2
23
Preliminary
0 (Default)
1 (Default)
OE_CTRL
(Pad #30)
3
OUTSEL0
Pad #25
22
4
1
0
21
0
1
0
1
65 mil
5
20
6
80 micron x 80 micron
Output enabled
Tri-state
Tri-state
Output enabled
PLL502-10
19
High Drive CMOS
Standard CMOS
PECL
LVDS
7
62 x 65 mil
Selected Output
18
8
Value
10 mil
GND
State
Rev 11/06/02 Page 1
12
11
10
17
16
15
14
13
9
(1550,1475)

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PLL502-10 Summary of contents

Page 1

... Wide pull range (+/-190 ppm) 3.3V operation. Available in DIE (65 mil x 62 mil). DESCRIPTIONS The PLL502- monolithic low jitter and low phase noise (-140dBc/Hz @ 10kHz offset) VCXO IC Die, with CMOS, LVDS and PECL output, covering the 750kHz to 400MHz output range. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal ...

Page 2

... Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved 0 0 Reserved 0 1 Reserved 1 0 Fin / Fin Reserved 0 1 Fin / Fin / Fin Fin / Fin Fin multiplication PLL502-10 Preliminary Selected Multiplier Rev 11/06/02 Page 2 ...

Page 3

... C at VCON = 1.65V L (xtal) AT cut (xtal cut E SYMBOL CONDITIONS T From power valid VCXOSTB 25MHz; XIN XTAL C /C < 250 VCON 3.3V 0V VCON 3.3V, -3dB PLL502-10 Preliminary MIN. MAX -0 -0 -65 150 S T -40 85 ...

Page 4

... Fout < 24MHz PECL/LVDS/CMOS 24MHz < Fout < 96MHz 96MHz < Fout < 400MHz @ 1.4V (CMOS) @ 1.25V (LVDS) @ Vdd – 1.3V (PECL) CONDITIONS FREQUENCY 19.44MHz 77.76MHz 155.52MHz 155.52MHz 155.52MHz @10Hz @100Hz -60 -90 -60 -90 -60 -90 PLL502-10 Preliminary MIN. TYP. MAX. 25/25/15 65/45/30 100/80/40 3.13 3. MIN. TYP. MAX. ...

Page 5

... I OSD SYMBOL CONDITIONS R = 100 (see figure LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80 DIFF 20 PLL502-10 Preliminary MIN. TYP. MAX. 247 355 454 -50 50 1.4 1.6 0.9 1.1 1.125 1.2 1.375 -5.7 -8 MIN. TYP. MAX. 0.2 0.7 1.0 0.2 0.7 1.0 LVDS Switching Test Circuit ...

Page 6

... V OL SYMBOL CONDITIONS @20/80% - PECL t r @80/20% - PECL t f PECL Output Skew VDD OUT 2.0V 50% OUT PECL Transistion Time Waveform DUTY CYCLE PLL502-10 Preliminary MIN. MAX. V – 1.025 DD V – 1.620 DD MIN. TYP. MAX. 0.6 1.5 0.5 1.5 t SKEW Rev 11/06/02 Page 6 UNITS V V UNITS ...

Page 7

... PLL502-10 Preliminary Rev 11/06/02 Page 7 ...

Page 8

... LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL502- PLL502-10 Preliminary TEMPERATURATRE C=COMMERCIAL M=MILITARY ...

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