74AUP2G38DC,125 NXP Semiconductors, 74AUP2G38DC,125 Datasheet - Page 17

IC NAND GATE DL 2-IN 8-VSSOP

74AUP2G38DC,125

Manufacturer Part Number
74AUP2G38DC,125
Description
IC NAND GATE DL 2-IN 8-VSSOP
Manufacturer
NXP Semiconductors
Series
74AUPr
Datasheet

Specifications of 74AUP2G38DC,125

Number Of Circuits
2
Package / Case
US8, 8-VSSOP
Logic Type
NAND Gate with Open Drain
Number Of Inputs
2
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
AUP
Low Level Output Current
4 mA
Propagation Delay Time
19.5 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AUP2G38DC-G
74AUP2G38DC-G
935280715125
NXP Semiconductors
Fig 16. Package outline SOT1203 (XSON8)
74AUP2G38
Product data sheet
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
mm
SOT1203
Unit
Outline
version
max
nom
min
0.35 0.04
A
(1)
A
1
terminal 1
index area
0.20
0.15
0.12
e
b
(8×)
IEC
L
(2)
1.40
1.35
1.30
1
D
1.05
1.00
0.95
E
1
8
0.55 0.35
e
JEDEC
e
1
All information provided in this document is subject to legal disclaimers.
2
7
e
1
References
e
D
Rev. 5 — 23 September 2010
1
0.35
0.30
0.27
0
L
3
6
0.40
0.35
0.32
e
L
1
1
JEITA
b
4
5
scale
0.5
A
E
L
Low-power dual 2-input NAND gate; open drain
1
A
1 mm
(4×)
(2)
European
projection
74AUP2G38
© NXP B.V. 2010. All rights reserved.
Issue date
10-04-02
10-04-06
sot1203_po
SOT1203
17 of 21

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