74LVC2G240GM,125 NXP Semiconductors, 74LVC2G240GM,125 Datasheet - Page 8
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74LVC2G240GM,125
Manufacturer Part Number
74LVC2G240GM,125
Description
IC INVERTER DUAL 4-INPUT 8QFN
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC2G240DC125.pdf
(22 pages)
Specifications of 74LVC2G240GM,125
Logic Type
Inverter
Number Of Inputs
1
Number Of Circuits
2
Current - Output High, Low
32mA, 32mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-XQFN
Logic Family
LVC
Number Of Channels Per Chip
2
Polarity
Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Low Level Output Current
32 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
2 / 2
Output Type
3-State
Propagation Delay Time
3 ns at 2.7 V, 2.5 ns at 3 V to 3.6 V, 2 ns at 4.5 V to 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC2G240GM-G
74LVC2G240GM-G
935282651125
74LVC2G240GM-G
935282651125
NXP Semiconductors
11. Dynamic characteristics
Table 8.
Voltages are referenced to GND (ground = 0 V); for test circuit see
[1]
[2]
[3]
[4]
[5]
74LVC2G240
Product data sheet
Symbol Parameter
t
t
t
C
pd
en
dis
PD
Typical values are measured at nominal V
t
t
t
C
P
f
f
C
V
N = number of inputs switching;
Σ(C
pd
en
dis
i
o
D
CC
PD
= input frequency in MHz;
L
= output frequency in MHz;
is the same as t
is the same as t
= output load capacitance in pF;
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
× V
propagation delay nA to nY; see
enable time
disable time
power dissipation
capacitance
PD
Dynamic characteristics
CC
× V
2
× f
CC
o
2
) = sum of outputs.
× f
PLH
PZH
PLZ
i
× N + Σ(C
and t
and t
and t
PHL
PZL
PHZ
Conditions
nOE to nY; see
nOE to nY; see
per buffer; V
L
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
output enabled
output disabled
× V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
2
× f
CC
o
All information provided in this document is subject to legal disclaimers.
) where:
I
= GND to V
and at T
Figure 7
Figure 8
Figure 8
Rev. 5 — 15 September 2010
amb
= 25 °C.
CC
D
in μW).
[2]
[3]
[4]
[5]
Figure
Min
1.0
0.5
1.0
0.5
0.5
1.5
1.0
1.5
0.5
0.5
1.0
0.5
1.0
1.0
0.5
-
-
−40 °C to +85 °C
9.
Dual inverting buffer/line driver; 3-state
Typ
4.1
2.6
3.0
2.5
2.0
4.5
2.9
3.4
2.5
2.0
3.5
1.9
2.8
2.7
1.9
18
5
[1]
Max
10.3
11.6
9.5
5.2
5.5
4.6
4.0
5.6
5.6
4.7
3.8
5.8
4.5
4.4
3.4
-
-
74LVC2G240
−40 °C to +125 °C Unit
Min
1.0
0.5
1.0
0.5
0.5
1.5
1.0
1.5
0.5
0.5
1.0
0.5
1.0
1.0
0.5
-
-
© NXP B.V. 2010. All rights reserved.
Max
12.9
14.1
11.9
6.5
6.9
5.8
5.0
7.0
7.0
5.9
4.8
7.6
5.8
5.7
4.6
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
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